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公开(公告)号：KR1020120132765A
公开(公告)日：2012-12-10
申请号：KR1020110051095
申请日：2011-05-30
Applicant: 삼성전자주식회사
CPC classification number: G06F11/1048 , G11C16/34 , G11C16/06
Abstract: PURPOSE: A nonvolatile memory device, an operating method thereof, and a memory system including the same are provided to secure integrity of a previous codeword even through an interrupt signal is generated in updating the previous codeword to a current codeword. CONSTITUTION: An access circuit(30) detects an interrupt signal in updating a previous codeword to a current codeword according to a program command, generates second parity bits using a part of the current codeword and previous codeword according to the detection result, and updates the first parity bits to the second parity bits. A capacitor supplies an operation voltage to an access circuit. An interrupt signal generating circuit(42) generates the interrupt signal in response to the detection signal from the voltage detector when an operation voltage is lower than a reference voltage.
Abstract translation: 目的：提供非易失性存储器件及其操作方法以及包括该非易失性存储器件的存储器系统，以便在将先前的代码字更新为当前的代码字时，即使通过中断信号来保证先前的代码字的完整性。 构成：根据程序命令，访问电路（30）检测将先前码字更新为当前码字的中断信号，根据检测结果使用当前码字和前一码字的一部分生成第二奇偶校验位，并更新 第一奇偶校验位到第二奇偶校验位。 电容器向接入电路提供工作电压。 当操作电压低于参考电压时，中断信号产生电路（42）响应于来自电压检测器的检测信号产生中断信号。
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公开(公告)号：KR1020120077521A
公开(公告)日：2012-07-10
申请号：KR1020100139501
申请日：2010-12-30
Applicant: 삼성전자주식회사
CPC classification number: H03M13/13 , G06F11/1044 , G06F11/1048 , G11C29/42
Abstract: PURPOSE: A memory device using an ECC(Error Correcting Code) and a system thereof are provided to effectively correct data errors regardless of time by using an additional memory device. CONSTITUTION: A memory system(100) includes a memory device(120) and a storage block. The memory device includes a normal cell region and an ECC cell region. The normal cell region includes memory cells for storing data bits. The ECC cell region includes ECC memory cells for storing ECC bits for the data bits. A storage block stores the ECC bits stored in the ECC cell region.
Abstract translation: 目的：提供使用ECC（纠错码）及其系统的存储器件，以通过使用附加存储器件来有效地校正数据错误，而不管时间如何。 构成：存储器系统（100）包括存储器件（120）和存储块。 存储器件包括正常单元区域和ECC单元区域。 正常单元区域包括用于存储数据位的存储单元。 ECC单元区域包括用于存储数据位的ECC位的ECC存储器单元。 存储块存储存储在ECC单元区域中的ECC位。
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公开(公告)号：KR1020120015166A
公开(公告)日：2012-02-21
申请号：KR1020100077450
申请日：2010-08-11
Applicant: 삼성전자주식회사
CPC classification number: G11C13/0069 , G11C13/0004 , G11C13/0007 , G11C2013/0088 , G11C2213/71 , G11C13/02 , G11C7/18 , G11C16/10 , G11C16/32
Abstract: PURPOSE: A memory device skimming bit sequence is provided to program the program bits in a unit cell array by using a bit sequence skim. CONSTITUTION: A plurality of unit cell arrays include a plurality of memory cells and are adjacently arranged. A program control block simultaneously programs one or more program bits in a corresponding memory cell by using a first program pulse. A plurality of local bit lines are connected to a global bit line. A memory cell array(12) includes a plurality of unit cell arrays(MG1 to MGi). Each unit cell array includes a plurality of nonvolatile memory cells(13).
Abstract translation: 目的：提供存储器件截取位序列，以通过使用位序列去除对单位单元阵列中的程序位进行编程。 构成：多个单元阵列包括多个存储单元并且相邻布置。 程序控制块通过使用第一编程脉冲同时对相应的存储单元中的一个或多个程序位进行编程。 多个局部位线连接到全局位线。 存储单元阵列（12）包括多个单元阵列（MG1至MGi）。 每个单元阵列包括多个非易失性存储单元（13）。
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公开(公告)号：KR1020110118874A
公开(公告)日：2011-11-02
申请号：KR1020100038246
申请日：2010-04-26
Applicant: 삼성전자주식회사
CPC classification number: G11C13/0069 , G11C13/0004 , G11C2013/0076 , G11C2013/0085 , G11C2213/72
Abstract: PURPOSE: A semiconductor device, a semiconductor system including the same, and an operation method thereof are provided to improve write speed by using the ratio of set current pulse width to reset current pulse width. CONSTITUTION: An access circuit(40) compares write data with the output data of a phase change memory cell(21) and generates a plurality of comparison signals. The access circuit writes a part of write data in the phase change memory cell. The access circuit comprises a plurality of comparison units The memory cell array(20) comprises a plurality of phase change memory cells.
Abstract translation: 目的：提供一种半导体器件，包括该半导体器件的半导体系统及其操作方法，以通过使用设定电流脉冲宽度与复位电流脉冲宽度的比来提高写入速度。 构成：访问电路（40）将写入数据与相变存储单元（21）的输出数据进行比较，并生成多个比较信号。 存取电路将写入数据的一部分写入相变存储单元。 所述存取电路包括多个比较单元。所述存储单元阵列（20）包括多个相变存储单元。
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公开(公告)号：KR1020110046808A
公开(公告)日：2011-05-06
申请号：KR1020090103476
申请日：2009-10-29
Applicant: 삼성전자주식회사
Inventor： 정회주
CPC classification number: G11C7/062 , G11C7/04 , G11C8/10 , G11C13/0004 , G11C13/0038 , G11C13/004 , G11C2207/063
Abstract: PURPOSE: A data read circuit including a phase change memory and an apparatuses having same are provided to secure the margin of a set state and a reset state to the change of an external temperature by reducing and shortening the amount of a lead current. CONSTITUTION: In a data read circuit including a phase change memory and an apparatuses having same, a variable current generating circuit(200) generates a variable current. The variable current varies is changed according to external temperature. A data sensing circuit(51) senses and amplifies data on a bit line. The bit line is connected to a nonvolatile memory. The data sensing circuit outputs sensed data. The sensing margin of data is controlled according to the amount of the variable current.
Abstract translation: 目的：提供包括相变存储器及其装置的数据读取电路，通过减少和缩短引线电流量来确保设定状态和复位状态的余量与外部温度的变化。 构成：在包括相变存储器的数据读取电路和具有相变存储器的装置中，可变电流产生电路（200）产生可变电流。 可变电流根据外部温度而变化。 数据感测电路（51）感测并放大位线上的数据。 位线连接到非易失性存储器。 数据检测电路输出感测数据。 数据的传感距离根据可变电流的数量来控制。
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Patent Agency Ranking
公开(公告)号：KR1020100083219A
公开(公告)日：2010-07-22
申请号：KR1020090002495
申请日：2009-01-13
Applicant: 삼성전자주식회사
Abstract: PURPOSE: A semiconductor device is provided to control one or at least two of a plurality of banks to be enabled by using a page size controller. CONSTITUTION: A memory cell array(50) comprises a plurality of banks. A page size controller(30) decode a part of a bank selection address, a part of power voltage, the rest of the bank selection address to control one or at least two banks to be enable. A chip selector(41) generates an enable signal for enabling a page size controller when a part of the bank select address and chip selection address are matched with a semiconductor ID.
Abstract translation: 目的：提供一种半导体器件，用于通过使用页面大小控制器来控制要启用的多个存储体中的一个或至少两个。 构成：存储单元阵列（50）包括多个存储体。 页面尺寸控制器（30）解码存储体选择地址的一部分，电源电压的一部分，存储体选择地址的其余部分，以控制一个或至少两个存储体被使能。 芯片选择器（41）当存储体选择地址和芯片选择地址的一部分与半导体ID相匹配时，生成使能信号，使能页大小控制器。
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公开(公告)号：KR1020090100024A
公开(公告)日：2009-09-23
申请号：KR1020080025379
申请日：2008-03-19
Applicant: 삼성전자주식회사
IPC: H01L27/10 , G11C11/4093
CPC classification number: G11C5/063 , G11C5/02 , H01L25/18 , H01L2924/0002 , H01L2924/00
Abstract: PURPOSE: A semiconductor memory device comprising a memory module of stacking memory chips are provided to reduce the length of a channel where a signal is transmitted. CONSTITUTION: A semiconductor memory device(300) has m substrate and n laminate memory. N laminate memory includes an n interface chip(n is the natural number) and a plurality of memory chips. N interface chip are connected to each substrate, and a plurality of memory chips are laminated on each interface chip in the vertical direction. A K-th interface chip(a k is the natural number less than n-1 over 1) of transmits a signal to the k+1 interface chip of connected to the same substrate.
Abstract translation: 目的：提供一种包括堆叠存储器芯片的存储器模块的半导体存储器件，以减少发送信号的通道的长度。 构成：半导体存储器件（300）具有m个衬底和n层压存储器。 N层叠存储器包括n个接口芯片（n是自然数）和多个存储器芯片。 N接口芯片连接到每个基板，并且在垂直方向上在每个接口芯片上层叠多个存储器芯片。 第k个接口芯片（k是小于n-1以上的自然数1）将信号发送到连接到同一基板的k + 1接口芯片。
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公开(公告)号：KR1020090100022A
公开(公告)日：2009-09-23
申请号：KR1020080025377
申请日：2008-03-19
Applicant: 삼성전자주식회사
Inventor： 정회주
IPC: G11C5/06
CPC classification number: G11C5/063 , G11C5/02 , H01L25/0657 , H01L2224/48091 , H01L2224/48227 , H01L2225/06527 , H01L2225/06541 , H01L2924/15311 , H01L2924/00014
Abstract: PURPOSE: A multi chip package memory compensating an amount of change of processes is provided to minimize power consumption by consuming the minimum power for operating each stacked memory chip. CONSTITUTION: A multi chip package memory(300) includes a transmission memory chip and first to n-th memory chips. The transmission memory chip outputs a reference signal corresponding to the amount of change of the processes. The first to n memory chips receive the reference signal. The first to n memory chips are vertically stacked on the transmission memory chip. The k memory chips control the amount of change of processes of the k memory chip in response to the reference signal.
Abstract translation: 目的：提供补偿处理量变化的多芯片封装存储器，以通过消耗用于操作每个堆叠的存储器芯片的最小功率来最小化功耗。 构成：多芯片封装存储器（300）包括传输存储器芯片和第一至第n个存储器芯片。 发送存储器芯片输出与处理的变化量相对应的参考信号。 第一到第n个存储器芯片接收参考信号。 第一至第n存储器芯片垂直堆叠在传输存储器芯片上。 k存储器芯片响应于参考信号来控制k存储器芯片的处理的变化量。
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公开(公告)号：KR1020090030407A
公开(公告)日：2009-03-25
申请号：KR1020070095685
申请日：2007-09-20
Applicant: 삼성전자주식회사
CPC classification number: G01R31/2884 , H01L23/60 , H01L27/0251 , H01L2924/0002 , H01L2924/00
Abstract: A semiconductor device and a method for testing the same are provided to reduce a size of a chip by reducing the number of test pad and the number of electrostatic discharge protection circuit. A test circuit(140) outputs a test control signal and a selection control signal in response to a test enable signal. An inner circuit(120) outputs a plurality of test signals by performing a fixed operation in response to the test control signal. A selection signal generating part(150) outputs a selection signal in response to the selection control signal. At least one multiplexer(160) receives a plurality of test signals, selects one among a plurality of test signals in response to the selection signal, and outputs the selection test signal. At least one test pad(TP) corresponds to at least one multiplexer, and receives the selection test signal. At least one electrostatic discharge protection circuit(110) is positioned between the multiplexer and the test pad, and discharges static electricity supplied through the test pad.
Abstract translation: 提供半导体器件及其测试方法，通过减少测试焊盘的数量和静电放电保护电路的数量来减小芯片的尺寸。 测试电路（140）响应于测试使能信号输出测试控制信号和选择控制信号。 内部电路（120）通过响应于测试控制信号执行固定操作来输出多个测试信号。 选择信号生成部（150）响应选择控制信号输出选择信号。 至少一个复用器（160）接收多个测试信号，响应于选择信号选择多个测试信号中的一个，并输出选择测试信号。 至少一个测试焊盘（TP）对应于至少一个复用器，并且接收选择测试信号。 至少一个静电放电保护电路（110）位于多路复用器和测试垫之间，并且释放通过测试垫提供的静电。
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110.发明授权
公开(公告)号：KR100825791B1
公开(公告)日：2008-04-29
申请号：KR1020060110182
申请日：2006-11-08
Applicant: 삼성전자주식회사
CPC classification number: G11C29/14 , G11C2029/5602 , G11C29/1201 , G11C7/10 , G11C29/56
Abstract: A high speed memory device capable of being tested easily using low speed ATE(Automatic Test Equipment) equipment and a method for controlling an input/output pin for the same are provided to perform unidirectional communication with the ATE through both of an 00B pin and a reflective 00B pin in a test mode. A bidirectional input/output pin is used for bidirectional communication. A mirrored bidirectional input/output pin has the same function as the bidirectional input/output pin. During normal operation, bidirectional communication with a host is performed through one of the bidirectional input/output pin and the mirrored bidirectional input/output pin. During test mode, unidirectional communication with test equipment(700) is performed through both of the bidirectional input/output pin and the mirrored bidirectional input/output pin.
Abstract translation: 提供能够使用低速ATE（自动测试设备）设备轻松测试的高速存储器件以及用于控制其输入/输出引脚的方法，以通过00B引脚和 反射00B针在测试模式。 双向输入/输出引脚用于双向通信。 镜像双向输入/输出引脚与双向输入/输出引脚功能相同。 在正常操作期间，通过双向输入/输出引脚和镜像双向输入/输出引脚之一执行与主机的双向通信。 在测试模式下，通过双向输入/输出引脚和镜像双向输入/输出引脚进行与测试设备（700）的单向通信。
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