정책 적용 손실을 최소화하기 위한 정책 기반 네트워크시스템 및 그 운영방법
    103.
    发明授权
    정책 적용 손실을 최소화하기 위한 정책 기반 네트워크시스템 및 그 운영방법 失效
    정책적용손실을최소하기위한정책기반네트워크시스템및그운영방

    公开(公告)号:KR100438896B1

    公开(公告)日:2004-07-02

    申请号:KR1020020015381

    申请日:2002-03-21

    Abstract: PURPOSE: A policy-based network system for minimizing the loss of policy enforcement and a method for operating the same are provided to minimize the loss of policy enforcement by supplying policy data to a policy client using a caching technique, even though a policy server fails to access a policy cache. CONSTITUTION: A policy-based network system is comprised of a PDP(Policy Decision Point)(104), a policy warehouse(105), and a PEP(Policy Enforcement Point)(102). The PEP(102), a policy client, having two interfaces for a sending terminal(101) and a receiving terminal(103), transfers data from the sending terminal(101) to the receiving terminal(103). The PDP(104), a policy server, decides the policy of the PEP(102) through a continuous connection with the PEP(102). In response to a policy decision request from the PEP(102), the PDP(104) searches the policy warehouse(105) for suitable policy data using an LDAP(Lightweight Directory Access Protocol). The PDP(104) comprises a cache warehouse(114) storing high-priority policy data for policy decision.

    Abstract translation: 目的:通过使用缓存技术向策略客户端提供策略数据,尽可能减少策略实施丢失的策略型网络系统及其操作方法,以最小化策略实施的损失,即使策略服务器失败 访问策略缓存。 组成:基于策略的网络系统由PDP(策略决策点)(104),策略仓库(105)和PEP(策略执行点)(102)组成。 具有用于发送终端(101)和接收终端(103)的两个接口的策略客户端PEP(102)将数据从发送终端(101)传送到接收终端(103)。 PDP(104)是策略服务器,通过与PEP(102)的连续连接来决定PEP(102)的策略。 响应于来自PEP(102)的策略决定请求,PDP(104)使用LDAP(轻量目录访问协议)在策略仓库(105)中搜索合适的策略数据。 PDP(104)包括存储用于策略决策的高优先级策略数据的高速缓存仓库(114)。

    디지털 처리 위상 고정 루프의 클록 동기 제어 방법
    104.
    发明公开
    디지털 처리 위상 고정 루프의 클록 동기 제어 방법 无效
    用于控制数字过程相位锁定环的时钟同步的方法

    公开(公告)号:KR1020040041981A

    公开(公告)日:2004-05-20

    申请号:KR1020020070094

    申请日:2002-11-12

    Inventor: 김봉수 이규호

    Abstract: PURPOSE: A method for controlling the clock synchronization of a digital process phase locked loop(PLL) is provided to reduce the time required for synchronizing the self generation clock with the external reference clock. CONSTITUTION: A method for controlling the clock synchronization of a digital process phase locked loop(PLL) includes the steps of: (a) determining(S401) whether or not the PLL is first performed; (b) if the PLL is first performed at step (a), storing(S405) the shift time shifting to the following step and the digital/analog control data on a non-volatile memory with performing the PLL; and (c) if the PLL is not first performed at step (a), performing(S409) the PLL during a time being shorter than the process time of the PLL at step (b) by using the shift time shifting to the following step and the digital/analog control data stored at step (b).

    Abstract translation: 目的:提供一种用于控制数字过程锁相环(PLL)的时钟同步的方法,以减少同步自产生时钟与外部参考时钟所需的时间。 构成:用于控制数字处理锁相环(PLL)的时钟同步的方法包括以下步骤:(a)确定(S401)是否首先执行PLL; (b)如果在步骤(a)中首先执行PLL,则通过执行PLL将(S405)移位到随后步骤的移位时间和数字/模拟控制数据存储在非易失性存储器上; 以及(c)如果在步骤(a)没有首先执行PLL,则在步骤(b)中通过使用转移到下一步骤的移位时间来执行(S409)PLL在比PLL处理时间短的时间内 以及在步骤(b)存储的数字/模拟控制数据。

    라우터 스위치 장치에서 라우팅 기능과 포워딩 기능을분리하는 방법 및 그 장치
    105.
    发明授权
    라우터 스위치 장치에서 라우팅 기능과 포워딩 기능을분리하는 방법 및 그 장치 失效
    라우터스위치장치에서라우팅기능과포워딩기능을분리하는방법및그장치

    公开(公告)号:KR100416508B1

    公开(公告)日:2004-01-31

    申请号:KR1020010086532

    申请日:2001-12-28

    Inventor: 김성혜 이규호

    Abstract: PURPOSE: A method for separating a routing function and a forwarding function in a router switch apparatus and an apparatus therefor are provided to classify the routing function and the forwarding function, and independently process general data except for routing data in a part for processing the forwarding function. CONSTITUTION: A routing information management unit receives a routing frame, generates and stores routing information, and receives and stores ARP(Address Resolution Protocol) information. Forwarding units(205,211) receive and store routing information from the routing information management unit(100), and receive a communication frame from an external communication network. If the communication frame is a routing frame, the forwarding units(205,211) provide the routing frame to the routing information management unit. If the communication frame is an ARP frame, the forwarding units(205,211) analyze the ARP frame, generate and store ARP information, and provide ARP information to the routing information management unit(100). If the communication frame is a general data frame, the forwarding units(205,211) extract the destination of the general data frame on the basis of routing information and ARP information, and transmit the general data frame to the destination. A switch unit(210) relays a data communication between the forwarding units(205,211) and between the forwarding units(205,211) and the routing information management unit(100).

    Abstract translation: 目的:提供一种路由器交换装置中的路由功能和转发功能的分离方法及其装置,用于对路由功能和转发功能进行分类,并且独立处理除了用于处理转发的部分中的路由数据之外的一般数据 功能。 构成:路由信息管理单元接收路由帧,产生并存储路由信息,并接收和存储ARP(地址解析协议)信息。 转发单元(205,211)接收并存储来自路由信息管理单元(100)的路由信息​​,并从外部通信网络接收通信帧。 如果通信帧是路由帧,则转发单元(205,211)将路由帧提供给路由信息管理单元。 如果通信帧是ARP帧,则转发单元(205,211)分析ARP帧,生成并存储ARP信息,并向路由信息管理单元(100)提供ARP信息。 如果通信帧是通用数据帧,则转发单元(205,211)基于路由信息和ARP信息提取通用数据帧的目的地,并将通用数据帧发送到目的地。 交换单元(210)中继转发单元(205,211)之间以及转发单元(205,211)和路由信息管理单元(100)之间的数据通信。

    다자간 통신에서의 액티브 네트워킹 기술을 이용한흐름제어 방법
    106.
    发明授权
    다자간 통신에서의 액티브 네트워킹 기술을 이용한흐름제어 방법 失效
    다자간통신에서의액티브네트워킹기술을이용한흐름제어방

    公开(公告)号:KR100383665B1

    公开(公告)日:2003-05-16

    申请号:KR1020000083261

    申请日:2000-12-27

    Abstract: PURPOSE: A method for controlling flow by using an active network technique in multipoint communication is provided to provide the scalability even though receivers are increased or are in a wide area, and minimize packet loss in even case that congested situation is generated within a network. CONSTITUTION: Data packets arrive at receivers and intermediate nodes(201). It is determined whether the packets are the first arrived packets of multicast communication(202). A soft storage in the node is initialized to start controlling multicast flow included in a program(203). Data packets arrived at the nodes, are saved at a buffer(204). An output port enabling transmission is searched(207). If data packet is in priority to be transmitted to the corresponding output port(208), data packet is duplicated ad transmitted to bottom nodes in case that the number of allowable credit to the corresponding bottom node is larger than 0(209). If the current node is the final receiver(205), packets are transmitted to an application layer and counter is increased by 1(206). If the counted value becomes a reference counter of flow control and a double number of credit update unit(211), the current node decides the amount of packets receivable from the top node based on the size of virtual buffer to each bottom node and generates credit packets including related information to the top node(213). It is determined whether data packets were transmitted to all corresponding output ports or the application layer(214).

    Abstract translation: 目的:提供一种在多点通信中通过使用主动网络技术来控制流的方法,以提供即使接收器增加或处于广域中也具有可扩展性,并且即使网络中产生拥塞情况也能使包丢失最小化。 构成:数据包到达接收机和中间节点(201)。 确定分组是否是多播通信的第一个到达的分组(202)。 初始化节点中的软存储器以开始控制包含在程序中的组播流(203)。 到达节点的数据包被保存在缓冲区(204)。 搜索(207)输出端口使能传输。 如果数据分组优先被发送到相应的输出端口(208),则在对应的底部节点的允许信用数量大于0的情况下,数据分组被复制和传输到底部节点(209)。 如果当前节点是最终接收器(205),则将分组发送到应用层并且将计数器增加1(206)。 如果计数值变为流量控制的参考计数器和双倍信用更新单元(211),则当前节点基于到每个底部节点的虚拟缓冲区的大小来确定从顶端节点可接收的分组量,并生成信用 将包括相关信息的分组发送给顶层节点(213)。 确定数据分组是否被发送到所有对应的输出端口或应用层(214)。

    이중포트램을 이용한 아이피 패킷 전달 장치 및 그 방법
    107.
    发明公开
    이중포트램을 이용한 아이피 패킷 전달 장치 및 그 방법 失效
    分组传输设备和使用双端口RAM的方法

    公开(公告)号:KR1020030016558A

    公开(公告)日:2003-03-03

    申请号:KR1020010050192

    申请日:2001-08-21

    CPC classification number: H04L12/5601

    Abstract: PURPOSE: A packet transferring device and a method using dual port ram are provided to speedup transferring of IP packets by using separate local bus and dual port ram. CONSTITUTION: The packet transferring device comprises a cell transferring element for transferring ATM(Asynchronous Transfer mode) cell; a cell processing elements which reconstruct the ATM cell received from the cell transferring element to send to a packet transferring element and then dividing the received IP packet from the packet transferring element to ATM cell to transmit to the cell transferring element; a packet transferring element which saves the IP packet transmitted from the cell processing element on a dual port ram packet memory and then transmitting the packet to the packet processing element via a IP packet receiving mode cue of a local memory; a packet processing element for processing the transmitted IP packet from the dual port ram packet memory according to a processing function of IP upper layer protocol. Wherein, the IP packet transferring element saves the IP packet processed form the packet processing element on the dual port ram packet memory and then transmits to the cell processing element via an IP packet transmitting buffer cue of the local memory.

    Abstract translation: 目的:提供数据包传输设备和使用双端口RAM的方法,通过使用单独的本地总线和双端口RAM来加速IP数据包的传输。 构成:分组传送装置包括用于传送ATM(异步传输模式)小区的小区传送单元; 重建从小区传送单元接收的ATM信元发送给分组传送单元,然后将接收到的分组从分组传送单元划分到ATM信元以发送给小区传送单元的小区处理单元; 分组传送单元,其将从所述单元处理单元发送的所述IP分组保存在双端口RAM分组存储器上,然后经由本地存储器的IP分组接收模式提示将所述分组发送到所述分组处理单元; 分组处理单元,用于根据IP上层协议的处理功能,从双端口RAM分组存储器处理发送的IP分组。 其中,IP分组传送单元将从分组处理单元处理的IP分组保存在双端口RAM分组存储器上,然后经由发送本地存储器的缓冲器提示的IP分组发送给小区处理单元。

    에이티엠 적응 계층 2에서 동적 결합 사용타이머(Timer_CU) 기반의 호 연결 제어 방법
    108.
    发明公开
    에이티엠 적응 계층 2에서 동적 결합 사용타이머(Timer_CU) 기반의 호 연결 제어 방법 失效
    用于控制ATM自适应层中动态组合使用定时器的呼叫连接的方法2

    公开(公告)号:KR1020030013709A

    公开(公告)日:2003-02-15

    申请号:KR1020010047861

    申请日:2001-08-09

    CPC classification number: H04L12/5601 H04L2012/5656

    Abstract: PURPOSE: A method for controlling a dynamic combined use timer based call connection in an ATM(asynchronous transfer mode) adaptive layer 2 is provided to minimize a consumption of a bandwidth by dynamically controlling a Time_CU value to reduce the time out number and use a remained bandwidth in a traffic for an available bit rate/unspecified bit rat service. CONSTITUTION: When a call is requested(S501), a cell assembly delay time is tested(S503). A Time_CU is increased(S505) and the cell assembly delay time is again tested(S507). The Time_CU is reduced to a previous value(S509) and a call request is received(S511). The Time_CU is compared with a MAX_TCU(S513). When the Time_CU is greater than the MAX_TCU, the call request is received(S511). When the Time_CU is less than the MAX_TCU, steps S505 to S513 are sequentially performed. The Time_CU is reduced(S515) and the cell assembly delay time is again tested(S517). The Time_CU is compared with a MIN_TCU(S519). When the Time_CU is greater than the MIN_TCU, the call request is rejected(S521). When the Time_CU is less than the MIN_TCU, steps S515 to S519 are sequentially performed.

    Abstract translation: 目的:提供一种用于控制ATM(异步传输模式)自适应层2中的基于动态组合使用定时器的呼叫连接的方法,以通过动态地控制Time_CU值来减少带宽的消耗以减少超时数并使用剩余 流量中的带宽用于可用比特率/未指定的比特老鼠服务。 构成:当请求呼叫(S501)时,测试单元组装延迟时间(S503)。 增加Time_CU(S505),再次测试单元组装延迟时间(S507)。 Time_CU减少到先前的值(S509),并且接收到呼叫请求(S511)。 将Time_CU与MAX_TCU进行比较(S513)。 当Time_CU大于MAX_TCU时,接收到呼叫请求(S511)。 当Time_CU小于MAX_TCU时,顺序执行步骤S505至S513。 Time_CU被减小(S515),再次测试单元组装延迟时间(S517)。 将Time_CU与MIN_TCU(S519)进行比较。 当Time_CU大于MIN_TCU时,呼叫请求被拒绝(S521)。 当Time_CU小于MIN_TCU时,顺序执行步骤S515至S519。

    공유 매체 액세스가 가능한 비동기 전달 모드 호스트 어뎁팅 장치
    109.
    发明公开
    공유 매체 액세스가 가능한 비동기 전달 모드 호스트 어뎁팅 장치 失效
    能够访问共享媒体的异步传送模式主机附加设备

    公开(公告)号:KR1019990053400A

    公开(公告)日:1999-07-15

    申请号:KR1019970073023

    申请日:1997-12-24

    Abstract: 1. 청구범위에 기재된 발명이 속하는 기술분야
    본 발명은 ATM 호스트 어뎁팅 장치에 관한 것임.
    2. 발명이 해결하고자하는 기술적 요지
    본 발명은 ATM 호스트에서 소정 주기마다 순간적으로 셀을 가산하여 공유 매체상의 트래픽 특성을 손상시키는 현상을 막을 수 있는 ATM 호스트 어뎁팅 장치를 제공하는데 그 목적이 있다.
    3. 발명의 해결 방법의 요지
    본 발명은 패킷 정보, 수신 셀 및 파라미터를 저장하고 있는 저장수단; 시스템 접속수단과, 마스터수단과, 슬레이브수단과, 프로세싱수단과, 정합수단과, 접속수단과, 중재수단을 갖는 망접속 조절수단; 및 상기 저장수단과 망 접속 조절수단을 접속하는 부접속수단을 포함한다.
    4. 발명의 중요한 용도
    본 발명은 일반적인 ATM 호스트 뿐만 아니라, 소규모 공유 매체 형태의 ATM 망에 접속된 ATM 장치에도 채용하는데 이용됨.

    로컬 메모리 중재 및 인터페이스 회로
    110.
    发明公开
    로컬 메모리 중재 및 인터페이스 회로 无效
    本地存储器仲裁和接口电路

    公开(公告)号:KR1019990043489A

    公开(公告)日:1999-06-15

    申请号:KR1019970064496

    申请日:1997-11-29

    Abstract: 본 발명은 ASIC 등의 회로에서 여러 기능 블럭이 외부의 메모리를 사용할 때 이 블럭간의 메모리 사용요구를 중재하여 처리하며 외부의 메모리의 속도에 상관없이 단일한 인터페이스를 제공하는 것을 목적으로 하며 본 발명은 읽기회로, 쓰기회로, 그리고 읽기/쓰기 중재회로로 나뉘어 지며, 읽기회로는 다시 읽기 중재회로, 읽기 타이밍 제어회로, 데이타 전달회로로 나뉘어 지고, 쓰기회로는 다시 쓰기 중재회로, 쓰기 타이밍 제어회로로 나뉘어 진다. 읽기회로와 쓰기회로는 외부 메모리와의 속도정합을 위하여 각각 FIFO를 가지고 있다.

Patent Agency Ranking