公开(公告)号：GB2219111A

公开(公告)日：1989-11-29

申请号：GB8912019

申请日：1989-05-25

Applicant: IBM

Inventor： BEGUN RALPH MURRAY ,  BLAND PATRICK MAURICE ,  DEAN MARK EDWARD

IPC: G06F12/08

Abstract: In a dual bus microcomputer system using a cache memory and a cache controller, the timing requirements placed on non-cache memory components by the cache controller are more stringent than the timing requirements placed on the non-cache memory components by the microprocessor. A logic circuit operates on the cache write enable (CWE) signals, and delays those signals in the event of a cache read miss. Delaying the CWE signals relaxes the timing requirements placed on non-cache memory components and at the same time does not impact wait state parameters for read miss operations.

公开(公告)号：NO891585A

公开(公告)日：1989-11-27

申请号：NO891585

申请日：1989-04-18

Applicant: IBM

Inventor： MILLING PHILIP ERNA ,  BLAND PATRICK MAURICE ,  DEAN MARK EDWARD

IPC: G06F13/36 ,  G06F13/362 ,  G06F12/06 ,  G06F13/38

CPC classification number: G06F13/36 ,  G06F13/362

公开(公告)号：NO891584A

公开(公告)日：1989-11-27

申请号：NO891584

申请日：1989-04-18

Applicant: IBM

Inventor： BEGUN RALPH MURRAY ,  BLAND PATRICK MAURICE ,  DEAN MARK EDWARD

IPC: G06F9/38 ,  G06F12/08 ,  G06F12/06

CPC classification number: G06F9/3802 ,  G06F12/0888

公开(公告)号：FI891786A

公开(公告)日：1989-11-27

申请号：FI891786

申请日：1989-04-14

Applicant: IBM

Inventor： MILLING PHILIP ERNA ,  DEAN MARK EDWARD ,  BLAND PATRICK MAURICE

IPC: G06F9/44 ,  G06F9/445 ,  G06F13/36 ,  G06F13/362 ,  G06F

Abstract: A multi-bus microcomputer system includes a cache subsystem and an arbitration supervisor. A CPU is provided with a PREEMPT signal source which generates a preempt signal in CPU cycles extending beyond a specified duration. The preempt signal is effective at any device having access to the bus to initiate an orderly termination of the bus usage. When that device signals its termination of bus usage, the arbitration supervisor changes the state of an ARB/GRANT conductor, which had been in the grant phase, to the arbitration phase. During the arbitration phase each of the devices (other than the CPU) cooperates in an arbitration mechanism for bus usage during the next grant phase. On the other hand, the CPU, having asserted preempt, responds to a signal indicating initiation of the arbitration phase by immediately accessing the system bus.

公开(公告)号：FI891785A

公开(公告)日：1989-11-27

申请号：FI891785

申请日：1989-04-14

Applicant: IBM

Inventor： BEGUN RALPH MURRAY ,  BLAND PATRICK MAURICE ,  DEAN MARK EDWARD

IPC: G06F12/08 ,  G06F

Abstract: A microcomputer system includes a microprocessor, a cache memroy, and a cache controller all coupled to a local bus. The local bus is coupled to a sytem bus, connecting the remaining system components, through latches. When writing data, the microcomputer can perform a posted write to a unit on the system bus by writing the data into the latches and then, on receipt of a ready signal from the cache controller, continuing its operations without waiting for the data to pas to its destination. A problem arises if the data is posted to a unit with a data width less than that of the microprocessor. In this case, the data should be sent in multiple cycles, but the read signal is generated before the data width of the unit is known and the microprocessor then continues its operations and can not, therefore, transmit the data correctly. To solve this problem, a logic unit is added to monitor the ready signal and the output of a decoder which detects non-cacheable addresses (which are of data width different from the microprocessor data width). If a non-cacheable address is detected, the read signal from the cache controller through the logic unit is withheld from the microprocessor, which now waits to continue processing beyond the write until a ready signal is received from the addressed unit on the system bus.

公开(公告)号：IT8920648D0

公开(公告)日：1989-05-25

申请号：IT2064889

申请日：1989-05-25

Applicant: IBM

Inventor： BEGUN RALPH MURRAY ,  BLAND PATRICK MAURICE ,  DEAN MARK EDWARD

IPC: G06F9/38 ,  G06F12/08

Abstract: In a microcomputer system comprising a microprocessor and a cache subsystem and operable in a pipelined mode, there is potential incompatibility between pipelined operations and dynamic bus sizing as the cache subsystem operates with a fixed size data width and dynamic bus sizing allows the system to operate with devices of differing data width. This incompatibility is accommodated by the present system by defining certain addresses as cacheable addresses and other addresses as non-cacheable addresses and ensuring that addresses of devices of data width different from the cache data width are non-cacheable. An address decoder provides a control signal indicating whether or not a generated address is within the cacheable range. This control signal controls a next address signal applied to the microprocessor, which signal allows the processor to proceed to a following cycle prior to the end of the current cycle. Whenever a non-cacheable address is detected, the next address signal is suppressed.

公开(公告)号：IT8920626D0

公开(公告)日：1989-05-24

申请号：IT2062689

申请日：1989-05-24

Applicant: IBM

Inventor： BLAND PATRICK MAURICE ,  DEAN MARK EDWARD ,  MILLING PHILLIP ERNA

IPC: G06F9/44 ,  G06F9/445 ,  G06F13/36 ,  G06F13/362

Abstract: A multi-bus microcomputer system includes a cache subsystem and an arbitration supervisor. A CPU is provided with a PREEMPT signal source which generates a preempt signal in CPU cycles extending beyond a specified duration. The preempt signal is effective at any device having access to the bus to initiate an orderly termination of the bus usage. When that device signals its termination of bus usage, the arbitration supervisor changes the state of an ARB/GRANT conductor, which had been in the grant phase, to the arbitration phase. During the arbitration phase each of the devices (other than the CPU) cooperates in an arbitration mechanism for bus usage during the next grant phase. On the other hand, the CPU, having asserted preempt, responds to a signal indicating initiation of the arbitration phase by immediately accessing the system bus.

公开(公告)号：DK189889D0

公开(公告)日：1989-04-19

申请号：DK189889

申请日：1989-04-19

Applicant: IBM

Inventor： BEGUN RALPH MURRAY ,  BLAND PATRICK MAURICE ,  DEAN MARK EDWARD

IPC: G06F9/44 ,  G06F9/445 ,  G06F13/36 ,  G06F13/362 ,  G06F13/00 ,  G06F12/00

Abstract: A multi-bus microcomputer system includes a cache subsystem and an arbitration supervisor. A CPU is provided with a PREEMPT signal source which generates a preempt signal in CPU cycles extending beyond a specified duration. The preempt signal is effective at any device having access to the bus to initiate an orderly termination of the bus usage. When that device signals its termination of bus usage, the arbitration supervisor changes the state of an ARB/GRANT conductor, which had been in the grant phase, to the arbitration phase. During the arbitration phase each of the devices (other than the CPU) cooperates in an arbitration mechanism for bus usage during the next grant phase. On the other hand, the CPU, having asserted preempt, responds to a signal indicating initiation of the arbitration phase by immediately accessing the system bus.

公开(公告)号：ZA845365B

公开(公告)日：1985-03-27

申请号：ZA845365

申请日：1984-07-11

Applicant: IBM

Inventor： BLAND PATRICK MAURICE ,  BOLT WILLIAM HAWKINS

IPC: H02J1/00 ,  G06F1/00 ,  G06F1/32 ,  G06F3/02 ,  G06F3/023 ,  G06F

Abstract: In a self-contained battery powered key entry device, the keyboard (2) is driven from a microprocessor (1) and its output sensed by the microprocessor to generate drive signals for an infra-red transmitter (24). The sense lines (DBO-DB7) are monitored so that, on a key depression, the microprocessor is switched to an operating mode from its low-power standby mode. When all sensed signals have been processed and outputted, the microprocessor is returned to the low-power standby mode. A delay may be incorporated.

公开(公告)号：DE69421453T2

公开(公告)日：2000-05-18

申请号：DE69421453

申请日：1994-05-25

Applicant: IBM

Inventor： AMINI NADER ,  BLAND PATRICK MAURICE ,  BOURY BECHARA FOUAD ,  HOFMANN RICHARD GERARD ,  LOHMAN TERENCE JOSEPH

IPC: G06F13/28 ,  G06F13/30 ,  G06F13/36 ,  G06F13/40

Abstract: A direct memory access (DMA) support mechanism is provided for use in a computer system 10 which comprises (i) a central processing unit (CPU) 24 connected to system memory 32 by a first system bus 36, and a second system bus 16 connected to the CPU; (ii) a host bridge 20 connecting the second system bus to a peripheral bus 22; (iii) an input/output (I/O) bridge 78 connecting the peripheral bus to a standard I/O bus 92, the standard I/O bus having a plurality of standard I/O devices 90 attached thereto; and (v) arbitration logic 42 which functions in an arbitration mode for arbitrating between the plurality of standard I/O devices competing for access to the standard I/O bus, and in a grant mode wherein a selected standard I/O device is granted access to the standard I/O bus. The DMA support mechanism comprises a direct memory access (DMA) controller 40 for performing DMA cycles on behalf of the selected standard I/O device, and direct memory access (DMA) support logic for enabling the DMA cycles to be performed over the peripheral bus. The DMA support logic includes sideband signals directly connecting the DMA controller with the I/O bridge, the sideband signals including information identifying the bus size of the selected I/O device for which the DMA controller is performing the DMA cycles.