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    Bus interface logic for computer system having dual bus architecture
    1.
    发明专利
    Bus interface logic for computer system having dual bus architecture 未知

    公开(公告)号：SG44432A1

    公开(公告)日：1997-12-19

    申请号：SG1996000366

    申请日：1992-12-22

    Applicant: IBM

    Inventor： ALDEREGULA ALFERDO ,  AMINI NADER ,  HORNE RICHARD LOUIS ,  LOHMAN TERENCE JOSEPH ,  TRAN CANG NGOC

    IPC: G06F13/16 ,  G06F13/36

    Abstract: A computer system is provided, comprising system memory and a memory controller for controlling access to system memory, a central processing unit electrically connected with the memory controller, and a bus interface unit electrically connected to the memory controller by a system bus and electrically connected to an input/output device by an input/output bus. The bus interface unit includes translation logic for temporarily storing, in response to a predetermined set of operating conditions, data transferred between the system bus and the input/output bus through the bus interface unit. The predetermined set of operating conditions occur when (i) the memory controller on behalf of the central processing unit writes data to the input/output device, or (ii) the memory controller on behalf of the central processing unit initiates a read or write cycle destined for the input/output device acting as a slave on the input/output bus, and the data bus width of the memory controller is greater than a corresponding data bus width of the input/output device.

    Bus control logic for computer system having dual bus architecture
    2.
    发明专利
    Bus control logic for computer system having dual bus architecture 未知

    公开(公告)号：AU663536B2

    公开(公告)日：1995-10-12

    申请号：AU2979292

    申请日：1992-12-02

    Applicant: IBM

    Inventor： AMINI NADER ,  BOURY BECHARA FOUAD ,  BRANNON SHERWOOD ,  HORNE RICHARD LOUIS ,  LOHMAN TERENCE JOSEPH

    IPC: G06F13/36 ,  G06F13/16 ,  G06F13/18 ,  G06F13/14

    Abstract: A computer system is provided, comprising system memory and a memory controller for controlling access to system memory by means of a memory bus, a central processing unit electrically connected with the memory controller for reading and writing data to the system memory over the memory bus, a bus interface unit electrically connected with the memory controller by means of a system bus, and an input/output device electrically connected to the bus interface unit by an input/output bus. The memory controller incorporates logic for arbitrating between the central processing unit and the input/output device to determine which of the central processing unit and the input/output device should be granted access to the system memory through said memory bus. The bus interface unit incorporates logic for overriding the memory controller logic, in response to a series of predetermined operating conditions, and grant exclusive access to system memory to the input/output device.

    Bus control logic computer system having dual bus architecture
    3.
    发明专利
    Bus control logic computer system having dual bus architecture 未知

    公开(公告)号：SG44430A1

    公开(公告)日：1997-12-19

    申请号：SG1996000358

    申请日：1992-12-18

    Applicant: IBM

    Inventor： AMINI NADER ,  BOURY BEECHARA FOUAD ,  BRANNON SHERWOOD ,  HORNE RICHARD LOUIS ,  LOHMAN TERENCE JOSEPH

    IPC: G06F13/36 ,  G06F13/16

    Abstract: A computer system is provided, comprising system memory and a memory controller for controlling access to system memory by means of a memory bus, a central processing unit electrically connected with the memory controller for reading and writing data to the system memory over the memory bus, a bus interface unit electrically connected with the memory controller by means of a system bus, and an input/output device electrically connected to the bus interface unit by an input/output bus. The memory controller incorporates logic for arbitrating between the central processing unit and the input/output device to determine which of the central processing unit and the input/output device should be granted access to the system memory through said memory bus. The bus interface unit incorporates logic for overriding the memory controller logic, in response to a series of predetermined operating conditions, and grant exclusive access to system memory to the input/output device.

    ARBITRATION LOGIC FOR MULTIPLE BUS COMPUTER SYSTEM
    4.
    发明专利
    ARBITRATION LOGIC FOR MULTIPLE BUS COMPUTER SYSTEM 未知

    公开(公告)号：CA2118995C

    公开(公告)日：1997-04-08

    申请号：CA2118995

    申请日：1994-03-14

    Applicant: IBM

    Inventor： AMINI NADER ,  BLAND PATRICK MAURICE ,  BOURY BECHARA FOUAD ,  HOFMANN RICHARD GERARD ,  LOHMAN TERENCE JOSEPH

    IPC: G06F13/36 ,  G06F13/362 ,  G06F13/364 ,  G06F13/40

    Abstract: An arbitration mechanism is provided for use in a computer system which comprises (i) a central processing unit (CPU); (ii) a first system bus which connects the CPU to system memory so that the CPU can read data from, and write data to, the system memory; (iii) a second system bus connected to the CPU; (iv) a host bridge connecting the second system bus to a peripheral bus, the peripheral bus having at least one peripheral device attached thereto; and (v) an input/output (I/O) bridge connecting the peripheral bus to a standard I/O bus, the standard I/O bus having a plurality of standard I/O devices attached thereto. The arbitration mechanism comprises (i) a first level of logic for arbitrating between the plurality of standard I/O devices, wherein one standard I/O device is selected from a plurality of the standard I/O devices competing for access to the standard I/O bus, and (ii) a second level of logic for arbitrating between the selected standard I/O device, the CPU and the at least one peripheral device, wherein one of the selected standard I/O device, the CPU and the at least one peripheral device is selected to access the peripheral bus. The arbitration mechanism includes sideband signals which connect the first and second levels of arbitration logic and include arbitration identification information corresponding to the selected standard I/O device.

    CPU BUS ALLOCATION CONTROL
    5.
    发明专利
    CPU BUS ALLOCATION CONTROL 未知

    公开(公告)号：CA2071306C

    公开(公告)日：1996-10-22

    申请号：CA2071306

    申请日：1992-06-16

    Applicant: IBM

    Inventor： BOURY BECHARA FOUAD ,  LOHMAN TERENCE JOSEPH ,  NGUYEN LONG DUY

    IPC: G06F13/18 ,  G06F13/30 ,  G06F13/362 ,  G06F13/366

    Abstract: An arbiter with first and second CPU timers is provided which advantageously allows measuring and controlling CPU bus ownership intervals via the arbiter. The first CPU timer, a running timer, specifies the total interval that the CPU is allocated the bus. The second timer, an idle timer, specifies an interval which the CPU may own the bus without performing an operation. The arbiter uses these two timers to dynamically adjust and control CPU bus ownership.

    7.
    发明专利
    未知

    公开(公告)号：BR9402105A

    公开(公告)日：1994-12-27

    申请号：BR9402105

    申请日：1994-05-27

    Applicant: IBM

    Inventor： AMINI NADER ,  BLAND PATRICK MAURICE ,  BOURY BECHARA FOUAD ,  HOFMANN RICHARD GERARD ,  LOHMAN TERENCE JOSEPH

    IPC: G06F13/28 ,  G06F13/30 ,  G06F13/36 ,  G06F13/40

    Abstract: A direct memory access (DMA) support mechanism is provided for use in a computer system 10 which comprises (i) a central processing unit (CPU) 24 connected to system memory 32 by a first system bus 36, and a second system bus 16 connected to the CPU; (ii) a host bridge 20 connecting the second system bus to a peripheral bus 22; (iii) an input/output (I/O) bridge 78 connecting the peripheral bus to a standard I/O bus 92, the standard I/O bus having a plurality of standard I/O devices 90 attached thereto; and (v) arbitration logic 42 which functions in an arbitration mode for arbitrating between the plurality of standard I/O devices competing for access to the standard I/O bus, and in a grant mode wherein a selected standard I/O device is granted access to the standard I/O bus. The DMA support mechanism comprises a direct memory access (DMA) controller 40 for performing DMA cycles on behalf of the selected standard I/O device, and direct memory access (DMA) support logic for enabling the DMA cycles to be performed over the peripheral bus. The DMA support logic includes sideband signals directly connecting the DMA controller with the I/O bridge, the sideband signals including information identifying the bus size of the selected I/O device for which the DMA controller is performing the DMA cycles.

    8.
    发明专利
    未知

    公开(公告)号：DE69421453D1

    公开(公告)日：1999-12-09

    申请号：DE69421453

    申请日：1994-05-25

    Applicant: IBM

    Inventor： AMINI NADER ,  BLAND PATRICK MAURICE ,  BOURY BECHARA FOUAD ,  HOFMANN RICHARD GERARD ,  LOHMAN TERENCE JOSEPH

    IPC: G06F13/28 ,  G06F13/30 ,  G06F13/36 ,  G06F13/40

    Abstract: A direct memory access (DMA) support mechanism is provided for use in a computer system 10 which comprises (i) a central processing unit (CPU) 24 connected to system memory 32 by a first system bus 36, and a second system bus 16 connected to the CPU; (ii) a host bridge 20 connecting the second system bus to a peripheral bus 22; (iii) an input/output (I/O) bridge 78 connecting the peripheral bus to a standard I/O bus 92, the standard I/O bus having a plurality of standard I/O devices 90 attached thereto; and (v) arbitration logic 42 which functions in an arbitration mode for arbitrating between the plurality of standard I/O devices competing for access to the standard I/O bus, and in a grant mode wherein a selected standard I/O device is granted access to the standard I/O bus. The DMA support mechanism comprises a direct memory access (DMA) controller 40 for performing DMA cycles on behalf of the selected standard I/O device, and direct memory access (DMA) support logic for enabling the DMA cycles to be performed over the peripheral bus. The DMA support logic includes sideband signals directly connecting the DMA controller with the I/O bridge, the sideband signals including information identifying the bus size of the selected I/O device for which the DMA controller is performing the DMA cycles.

    ARBITRATION CONTROL LOGIC FOR COMPUTER SYSTEM HAVING FULL BUS ARCHITECTURE
    10.
    发明专利
    ARBITRATION CONTROL LOGIC FOR COMPUTER SYSTEM HAVING FULL BUS ARCHITECTURE 未知

    公开(公告)号：CA2080630C

    公开(公告)日：1996-10-22

    申请号：CA2080630

    申请日：1992-10-15

    Applicant: IBM

    Inventor： AMINI NADER ,  BOURY BECHARA FOUAD ,  HORNE RICHARD LOUIS ,  LOHMAN TERENCE JOSEPH

    IPC: G06F13/28 ,  G06F13/22 ,  G06F13/36 ,  G06F13/362 ,  G06F13/16 ,  G06F13/18 ,  G06F13/20

    Abstract: A computer system is provided comprising system memory and a memory controller for controlling access to system memory, a central processing unit electrically connected with the memory controller, and a bus interface unit electrically connected to the memory controller by a system bus and electrically connected to a plurality of input/output devices by an input/output bus. The bus interface unit is able to sense when said one of said input/output devices has completed a read or write operation over said input/output bus, and includes a buffer circuit wherein read and write data transferred between the system bus and the input/output bus via the bus interface unit is temporarily stored during the transfer. Arbitration control logic resides in said bus interface unit and interacts with a central arbitration controller which resides on the system bus. The central arbitration controller responds to the arbitration control logic to simultaneously perform (i) arbitration cycles wherein the central arbitration controller arbitrates between the plurality of input/output devices and the central processing unit to determine which of the input/output devices or the central processing unit should be granted control of the input/output bus and (ii) grant cycles wherein the central arbitration controller grants control of the input/output bus and extends control of the system bus to one of the input/output devices or the central processing unit.

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