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公开(公告)号：DE69421453T2
公开(公告)日：2000-05-18
申请号：DE69421453
申请日：1994-05-25
Applicant: IBM
Inventor： AMINI NADER , BLAND PATRICK MAURICE , BOURY BECHARA FOUAD , HOFMANN RICHARD GERARD , LOHMAN TERENCE JOSEPH
Abstract: A direct memory access (DMA) support mechanism is provided for use in a computer system 10 which comprises (i) a central processing unit (CPU) 24 connected to system memory 32 by a first system bus 36, and a second system bus 16 connected to the CPU; (ii) a host bridge 20 connecting the second system bus to a peripheral bus 22; (iii) an input/output (I/O) bridge 78 connecting the peripheral bus to a standard I/O bus 92, the standard I/O bus having a plurality of standard I/O devices 90 attached thereto; and (v) arbitration logic 42 which functions in an arbitration mode for arbitrating between the plurality of standard I/O devices competing for access to the standard I/O bus, and in a grant mode wherein a selected standard I/O device is granted access to the standard I/O bus. The DMA support mechanism comprises a direct memory access (DMA) controller 40 for performing DMA cycles on behalf of the selected standard I/O device, and direct memory access (DMA) support logic for enabling the DMA cycles to be performed over the peripheral bus. The DMA support logic includes sideband signals directly connecting the DMA controller with the I/O bridge, the sideband signals including information identifying the bus size of the selected I/O device for which the DMA controller is performing the DMA cycles.
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公开(公告)号：AT186412T
公开(公告)日：1999-11-15
申请号：AT94303783
申请日：1994-05-25
Applicant: IBM
Inventor： AMINI NADER , BLAND PATRICK MAURICE , BOURY BECHARA FOUAD , HOFMANN RICHARD GERARD , LOHMAN TERENCE JOSEPH
Abstract: A direct memory access (DMA) support mechanism is provided for use in a computer system 10 which comprises (i) a central processing unit (CPU) 24 connected to system memory 32 by a first system bus 36, and a second system bus 16 connected to the CPU; (ii) a host bridge 20 connecting the second system bus to a peripheral bus 22; (iii) an input/output (I/O) bridge 78 connecting the peripheral bus to a standard I/O bus 92, the standard I/O bus having a plurality of standard I/O devices 90 attached thereto; and (v) arbitration logic 42 which functions in an arbitration mode for arbitrating between the plurality of standard I/O devices competing for access to the standard I/O bus, and in a grant mode wherein a selected standard I/O device is granted access to the standard I/O bus. The DMA support mechanism comprises a direct memory access (DMA) controller 40 for performing DMA cycles on behalf of the selected standard I/O device, and direct memory access (DMA) support logic for enabling the DMA cycles to be performed over the peripheral bus. The DMA support logic includes sideband signals directly connecting the DMA controller with the I/O bridge, the sideband signals including information identifying the bus size of the selected I/O device for which the DMA controller is performing the DMA cycles.
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公开(公告)号：PL320022A1
公开(公告)日：1997-09-01
申请号：PL32002295
申请日：1995-11-27
Applicant: IBM
Inventor： BLAND PATRICK MAURICE , CRONIN DANIEL RAYMOND , HOFMANN RICHARD GERARD , MOELLER DENNIS , VENARCHICK LANCE MICHAEL
Abstract: A computer system that has two buses (30, 32) with different memory addressing capacities and a first bus master (36) that generates M-bit addresses is provided with a bridge (34) between the two buses. In order to generate N-bit addresses for use on the second bus (30), a direct memory access (DMA) controller (50) on the bridge produces P bits, where P + M = N. The P bits are concentrated with the M bits to form an N-bit address used on the second bus (30) to address memory (40). The addition of P bits reallocates the memory segment addressable by the M-bits to any location within the memory map addressable by an N-bit address.
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公开(公告)号：DE69423056T2
公开(公告)日：2000-09-14
申请号：DE69423056
申请日：1994-05-25
Applicant: IBM
Inventor： AMINI NADER , BLAND PATRICK MAURICE , BOURY BECHARA FOUAD , HOFMANN RICHARD GERARD , LOHMAN TERENCE JOSEPH
IPC: G06F13/36 , G06F13/362 , G06F13/364 , G06F13/40
Abstract: An arbitration mechanism 42 is provided for use in a computer system 10 which comprises (i) a central processing unit (CPU) 24; (ii) a first system bus 36 which connects the CPU 24 to system memory 32 so that the CPU 24 can read data from, and write data to, the system memory 32; (iii) a second system bus 16 connected to the CPU 24; (iv) a host bridge 20 connecting the second-system bus 16 to a peripheral bus 22, the peripheral bus 22 having at least one peripheral device 18 attached thereto; and (v) an input/output (I/O) bridge 78 connecting the peripheral bus 22 to a standard I/O bus 92, the standard I/O bus 92 having a plurality of standard I/O devices 90 attached thereto. The arbitration mechanism 42 comprises (i) a first level 100 of logic for arbitrating between the plurality of standard I/O devices 90, wherein one standard I/O device 90 is selected from a plurality of the standard I/O devices 90 competing for access to the standard I/O bus 97, and (ii) a second level 102, 104 of logic for arbitrating between the selected standard I/O device 90, the CPU 24 and the at least one peripheral device 18, wherein one of the selected standard I/O device 90, the CPU 24 and the at least one peripheral device 18 is selected to access the peripheral bus 22. The arbitration mechanism 42 includes sideband signals which connect the first 100 and second levels 102, 104 of arbitration logic and include arbitration identification information corresponding to the selected standard I/O device 90.
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公开(公告)号：DE69423056D1
公开(公告)日：2000-03-30
申请号：DE69423056
申请日：1994-05-25
Applicant: IBM
Inventor： AMINI NADER , BLAND PATRICK MAURICE , BOURY BECHARA FOUAD , HOFMANN RICHARD GERARD , LOHMAN TERENCE JOSEPH
IPC: G06F13/36 , G06F13/362 , G06F13/364 , G06F13/40
Abstract: An arbitration mechanism 42 is provided for use in a computer system 10 which comprises (i) a central processing unit (CPU) 24; (ii) a first system bus 36 which connects the CPU 24 to system memory 32 so that the CPU 24 can read data from, and write data to, the system memory 32; (iii) a second system bus 16 connected to the CPU 24; (iv) a host bridge 20 connecting the second-system bus 16 to a peripheral bus 22, the peripheral bus 22 having at least one peripheral device 18 attached thereto; and (v) an input/output (I/O) bridge 78 connecting the peripheral bus 22 to a standard I/O bus 92, the standard I/O bus 92 having a plurality of standard I/O devices 90 attached thereto. The arbitration mechanism 42 comprises (i) a first level 100 of logic for arbitrating between the plurality of standard I/O devices 90, wherein one standard I/O device 90 is selected from a plurality of the standard I/O devices 90 competing for access to the standard I/O bus 97, and (ii) a second level 102, 104 of logic for arbitrating between the selected standard I/O device 90, the CPU 24 and the at least one peripheral device 18, wherein one of the selected standard I/O device 90, the CPU 24 and the at least one peripheral device 18 is selected to access the peripheral bus 22. The arbitration mechanism 42 includes sideband signals which connect the first 100 and second levels 102, 104 of arbitration logic and include arbitration identification information corresponding to the selected standard I/O device 90.
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Patent Agency Ranking
公开(公告)号：DE69421453D1
公开(公告)日：1999-12-09
申请号：DE69421453
申请日：1994-05-25
Applicant: IBM
Inventor： AMINI NADER , BLAND PATRICK MAURICE , BOURY BECHARA FOUAD , HOFMANN RICHARD GERARD , LOHMAN TERENCE JOSEPH
Abstract: A direct memory access (DMA) support mechanism is provided for use in a computer system 10 which comprises (i) a central processing unit (CPU) 24 connected to system memory 32 by a first system bus 36, and a second system bus 16 connected to the CPU; (ii) a host bridge 20 connecting the second system bus to a peripheral bus 22; (iii) an input/output (I/O) bridge 78 connecting the peripheral bus to a standard I/O bus 92, the standard I/O bus having a plurality of standard I/O devices 90 attached thereto; and (v) arbitration logic 42 which functions in an arbitration mode for arbitrating between the plurality of standard I/O devices competing for access to the standard I/O bus, and in a grant mode wherein a selected standard I/O device is granted access to the standard I/O bus. The DMA support mechanism comprises a direct memory access (DMA) controller 40 for performing DMA cycles on behalf of the selected standard I/O device, and direct memory access (DMA) support logic for enabling the DMA cycles to be performed over the peripheral bus. The DMA support logic includes sideband signals directly connecting the DMA controller with the I/O bridge, the sideband signals including information identifying the bus size of the selected I/O device for which the DMA controller is performing the DMA cycles.
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公开(公告)号：HUT76725A
公开(公告)日：1997-11-28
申请号：HU9701328
申请日：1995-11-27
Applicant: IBM
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公开(公告)号：CA2118995C
公开(公告)日：1997-04-08
申请号：CA2118995
申请日：1994-03-14
Applicant: IBM
Inventor： AMINI NADER , BLAND PATRICK MAURICE , BOURY BECHARA FOUAD , HOFMANN RICHARD GERARD , LOHMAN TERENCE JOSEPH
IPC: G06F13/36 , G06F13/362 , G06F13/364 , G06F13/40
Abstract: An arbitration mechanism is provided for use in a computer system which comprises (i) a central processing unit (CPU); (ii) a first system bus which connects the CPU to system memory so that the CPU can read data from, and write data to, the system memory; (iii) a second system bus connected to the CPU; (iv) a host bridge connecting the second system bus to a peripheral bus, the peripheral bus having at least one peripheral device attached thereto; and (v) an input/output (I/O) bridge connecting the peripheral bus to a standard I/O bus, the standard I/O bus having a plurality of standard I/O devices attached thereto. The arbitration mechanism comprises (i) a first level of logic for arbitrating between the plurality of standard I/O devices, wherein one standard I/O device is selected from a plurality of the standard I/O devices competing for access to the standard I/O bus, and (ii) a second level of logic for arbitrating between the selected standard I/O device, the CPU and the at least one peripheral device, wherein one of the selected standard I/O device, the CPU and the at least one peripheral device is selected to access the peripheral bus. The arbitration mechanism includes sideband signals which connect the first and second levels of arbitration logic and include arbitration identification information corresponding to the selected standard I/O device.
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公开(公告)号：BR9402105A
公开(公告)日：1994-12-27
申请号：BR9402105
申请日：1994-05-27
Applicant: IBM
Inventor： AMINI NADER , BLAND PATRICK MAURICE , BOURY BECHARA FOUAD , HOFMANN RICHARD GERARD , LOHMAN TERENCE JOSEPH
Abstract: A direct memory access (DMA) support mechanism is provided for use in a computer system 10 which comprises (i) a central processing unit (CPU) 24 connected to system memory 32 by a first system bus 36, and a second system bus 16 connected to the CPU; (ii) a host bridge 20 connecting the second system bus to a peripheral bus 22; (iii) an input/output (I/O) bridge 78 connecting the peripheral bus to a standard I/O bus 92, the standard I/O bus having a plurality of standard I/O devices 90 attached thereto; and (v) arbitration logic 42 which functions in an arbitration mode for arbitrating between the plurality of standard I/O devices competing for access to the standard I/O bus, and in a grant mode wherein a selected standard I/O device is granted access to the standard I/O bus. The DMA support mechanism comprises a direct memory access (DMA) controller 40 for performing DMA cycles on behalf of the selected standard I/O device, and direct memory access (DMA) support logic for enabling the DMA cycles to be performed over the peripheral bus. The DMA support logic includes sideband signals directly connecting the DMA controller with the I/O bridge, the sideband signals including information identifying the bus size of the selected I/O device for which the DMA controller is performing the DMA cycles.
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公开(公告)号：BR9203849A
公开(公告)日：1993-05-04
申请号：BR9203849
申请日：1992-10-02
Applicant: IBM
Inventor： AMINI NADER , BOURY BECHARA FOUAD , BRANNON SHERWOOD , HOFMANN RICHARD GERARD , LOHMAN TERENCE J
Abstract: A DMA controller with error circuitry which detects DMA error conditions is disclosed. The error circuitry causes the DMA controller to perform completion tasks before terminating a DMA transfer, advantageously providing a DMA controller which may exit gracefully upon detection of an error condition with the potential of error recovery.
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