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    METHODS AND APPARATUS TO ASSIGN WORKLOADS BASED ON EMISSIONS ESTIMATES
    101.
    发明公开
    METHODS AND APPARATUS TO ASSIGN WORKLOADS BASED ON EMISSIONS ESTIMATES 审中-公开

    公开(公告)号：US20240193617A1

    公开(公告)日：2024-06-13

    申请号：US18542370

    申请日：2023-12-15

    Applicant: Intel Corporation

    Inventor： Francesc Guim Bernat ,  Karthik Kumar ,  Akhilesh S. Thyagaturu ,  Thijs Metsch ,  Adrian Hoban

    IPC: G06Q30/018 ,  G06F9/50

    CPC classification number: G06Q30/018 ,  G06F9/505

    Abstract: Systems, apparatus, articles of manufacture, and methods are disclosed. An example apparatus includes programmable circuitry to at least: obtain a first response associated with an estimate of emissions to be produced by execution of a workload on first hardware; obtain a second response associated with an estimate of emissions to be produced by execution of the workload on second hardware; and assign one of the first or the second hardware to execute the workload based on the first response and the second response, the assigned one of the first or the second hardware to at least one of utilize more time or more memory to execute the workload than the other of the first or the second hardware.

    ALLOCATION OF ACCESS TO A CHIPLET ACROSS AN INTERCONNECT SWITCH
    102.
    发明公开
    ALLOCATION OF ACCESS TO A CHIPLET ACROSS AN INTERCONNECT SWITCH 审中-公开

    公开(公告)号：US20240193284A1

    公开(公告)日：2024-06-13

    申请号：US18080635

    申请日：2022-12-13

    Applicant: Intel Corporation

    Inventor： Francesc Guim Bernat ,  Marcos Carranza ,  Kshitij Doshi ,  Ned Smith ,  Karthik Kumar

    IPC: G06F21/60

    CPC classification number: G06F21/604

    Abstract: Techniques and mechanisms to allocate functionality of a chiplet for access by one or more processor cores which are coupled to remote processor via a network switch. In an embodiment, a composite chip communicates with the switch via a Compute Express Link (CXL) link. The switch receives capability information which identifies both a chiplet of the composite chip, and a functionality which is available from a resource of that chiplet. Based on the capability information, the switch provides an inventory of chiplet resources. In response to an allocation request, the switch accesses the inventory to identify whether a suitable chiplet resource is available. Based on the access, the switch configures a chip to enable an allocation of a chiplet resource. In another embodiment, the chiplet resource is allocated at a sub-processor level of granularity, and disables access to the chiplet resource by one or more local processor cores.

    Quality of service rules in allocating processor resources
    104.
    发明授权
    Quality of service rules in allocating processor resources 有权

    公开(公告)号：US11972291B2

    公开(公告)日：2024-04-30

    申请号：US16728865

    申请日：2019-12-27

    Applicant: Intel Corporation

    Inventor： Francesc Guim ,  Karthik Kumar ,  Mustafa Hajeer ,  Tushar Gohad

    IPC: G06F9/50 ,  G06F11/34

    CPC classification number: G06F9/5011 ,  G06F11/3409

    Abstract: An apparatus and method for conditional quality of service in a processor. For example, one embodiment of a processor comprises: a plurality of processor resources to be allocated to a plurality of executed processes in accordance with a set of quality of service (QoS) rules; and conditional quality of service (QoS) circuitry/logic to monitor usage of the plurality of processor resources by the plurality of processes and to responsively modify an allocation of a first processor resource for a first process in response to detecting a first threshold value being reached in a second resource allocated to the first process.

    Data management for edge architectures
    110.
    发明授权
    Data management for edge architectures 有权

    公开(公告)号：US11797343B2

    公开(公告)日：2023-10-24

    申请号：US17401652

    申请日：2021-08-13

    Applicant: Intel Corporation

    Inventor： Francesc Guim Bernat ,  Ramanathan Sethuraman ,  Karthik Kumar ,  Mark A. Schmisseur ,  Brinda Ganesh

    IPC: G06F9/50 ,  G06F9/54

    CPC classification number: G06F9/5011 ,  G06F9/542

    Abstract: Data management for edge architected computing systems extends current storage and memory schemes of edge resources to expose interfaces to allow a device, such as an endpoint or client device, or another edge resource, to specify criteria for managing data originating from the device and stored in an edge resource, and extends the storage and memory controllers to manage data in accordance with the criteria, including removing stored data that no longer satisfies the criteria. The criteria includes a temporal hint to specify a time after which the data can be removed, a physical hint to specify a list of edge resources outside of which the data can be removed, an event-based hint to specify an event after which the data can be removed, and a quality of service condition to modify the time specified in the temporal hint based on a condition, such as memory and storage capacity of the edge resource in which the data is managed.

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