公开(公告)号：US20210110310A1

公开(公告)日：2021-04-15

申请号：US17131462

申请日：2020-12-22

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Ned M. Smith ,  Karthik Kumar ,  Sunil Cheruvu ,  Timothy Verrall

IPC: G06N20/00 ,  G06F16/27 ,  H04L29/06

Abstract: Methods and apparatus to verify trained models in edge environments are disclosed. An example apparatus to validate a trained model in an edge environment includes an attestation verifier to determine an attestation score of the model received at a first appliance, the attestation score calculated at a second appliance different from the first appliance, a comparator to compare the attestation score to a threshold, a validator to validate the model based on the comparison, and an executor to at least one of execute or deploy the model based on the validation.

公开(公告)号：US20210044646A1

公开(公告)日：2021-02-11

申请号：US17069809

申请日：2020-10-13

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Brinda Ganesh ,  Timothy Verrall ,  Ned Smith ,  Kshitij Doshi

IPC: H04L29/08 ,  G06F9/455

Abstract: Methods, apparatus, systems and articles of manufacture for re-use of a container in an edge computing environment are disclosed. An example method includes detecting that a container executed at an edge node of a cloud computing environment is to be cleaned, deleting user data from the container, the deletion of the user data performed without deleting the container from the memory of the edge node, restoring settings of the container to a default state; and storing information identifying the container, the information including a flavor of the container, the storing of the information to enable the container to be re-used by a subsequent requestor.

公开(公告)号：US20210014133A1

公开(公告)日：2021-01-14

申请号：US17032993

申请日：2020-09-25

Applicant: Intel Corporation

Inventor： Christian Maciocco ,  Kshitij Doshi ,  Francesc Guim Bernat ,  Ned M. Smith ,  Marcin Spoczynski ,  Timothy Verrall ,  Rajesh Gadiyar ,  Trevor Cooper ,  Valerie Parker

IPC: H04L12/24 ,  H04L12/26 ,  H04L29/08

Abstract: Methods and apparatus to coordinate edge platforms are disclosed. A disclosed example apparatus includes to control processing of data associated with edges includes an orchestrator analyzer to determine a first performance requirement of a first microservice of an application and a second performance requirement of a second microservice of the application. The apparatus also includes an orchestrator controller to assign the first microservice and the second microservice across first and second edge nodes between a source network and a destination network by: assigning the first microservice to the first edge node based on a first capability of the first edge node satisfying the first performance requirement of the first microservice, and assigning the second microservice to the second edge node based on a second capability of the second edge node satisfying the second performance requirement of the second microservice.

公开(公告)号：US20200076682A1

公开(公告)日：2020-03-05

申请号：US16367626

申请日：2019-03-28

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Karthik Kumar ,  Benjamin Graniello ,  Timothy Verrall ,  Andrew J. Herdrich ,  Rashmin Patel ,  Monica Kenguva ,  Brinda Ganesh ,  Alexander Vul ,  Ned M. Smith ,  Suraj Prabhakaran

IPC: H04L12/24

Abstract: Technologies for providing multi-tenant support in edge resources using edge channels include a device that includes circuitry to obtain a message associated with a service provided at the edge of a network. Additionally, the circuitry is to identify an edge channel based on metadata associated with the message. The edge channel has a predefined amount of resource capacity allocated to the edge channel to process the message. Further, the circuitry is to determine the predefined amount of resource capacity allocated to the edge channel and process the message using the allocated resource capacity for the identified edge channel.

公开(公告)号：US20190394081A1

公开(公告)日：2019-12-26

申请号：US16015247

申请日：2018-06-22

Applicant: Intel Corporation

Inventor： Maryam Tahhan ,  John Joseph Browne ,  Eoin Walsh ,  Timothy Verrall ,  Rory Browne ,  Emma Louise Foley ,  Shobhi Jain ,  Peter Mangan

IPC: H04L12/24 ,  H04L12/26

Abstract: There is disclosed in one example a computing apparatus, including: a local platform including a hardware platform; a management interface to communicatively couple the local platform to a management controller; a virtualization infrastructure to operate on the hardware platform and to provide a local virtualized function; and a resiliency controller to operate on the hardware platform, and configured to: receive a resiliency policy from the management controller via the management interface, the resiliency policy including information to handle a fault in the virtualized function; detect a fault in the local virtualized function; and effect a resiliency action responsive to detecting the fault.

公开(公告)号：US20190391855A1

公开(公告)日：2019-12-26

申请号：US16563171

申请日：2019-09-06

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Karthik Kumar ,  Suraj Prabhakaran ,  Timothy Verrall ,  Thomas Willhalm ,  Mark Schmisseur

IPC: G06F9/50 ,  H04L9/08 ,  G06F21/60 ,  G06F16/27

Abstract: Technologies for providing efficient data access in an edge infrastructure include a compute device comprising circuitry configured to identify pools of resources that are usable to access data at an edge location. The circuitry is also configured to receive a request to execute a function at an edge location. The request identifies a data access performance target for the function. The circuitry is also configured to map, based on a data access performance of each pool and the data access performance target of the function, the function to a set of the pools to satisfy the data access performance target.

公开(公告)号：US20190229897A1

公开(公告)日：2019-07-25

申请号：US16368982

申请日：2019-03-29

Applicant: Intel Corporation

Inventor： Timothy Verrall ,  Thomas Willhalm ,  Francesc Guim Bernat ,  Karthik Kumar ,  Ned M. Smith ,  Rajesh Poornachandran ,  Kapil Sood ,  Tarun Viswanathan ,  John J. Browne ,  Patrick Kutch

IPC: H04L9/08

Abstract: Technologies for accelerated key caching in an edge hierarchy include multiple edge appliance devices organized in tiers. An edge appliance device receives a request for a key, such as a private key. The edge appliance device determines whether the key is included in a local key cache and, if not, requests the key from an edge appliance device included in an inner tier of the edge hierarchy. The edge appliance device may request the key from an edge appliance device included in a peer tier of the edge hierarchy. The edge appliance device may activate per-tenant accelerated logic to identify one or more keys in the key cache for eviction. The edge appliance device may activate per-tenant accelerated logic to identify one or more keys for pre-fetching. Those functions of the edge appliance device may be performed by an accelerator such as an FPGA. Other embodiments are described and claimed.

公开(公告)号：US20190220210A1

公开(公告)日：2019-07-18

申请号：US16368152

申请日：2019-03-28

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Karthik Kumar ,  Thomas Willhalm ,  Timothy Verrall ,  Ned Smith

IPC: G06F3/06 ,  G06F12/02 ,  G06F17/17 ,  G06F12/1072 ,  G06F16/901

CPC classification number: G06F3/0641 ,  G06F3/0608 ,  G06F3/067 ,  G06F12/0292 ,  G06F12/1072 ,  G06F16/9014 ,  G06F17/17

Abstract: Technologies for providing deduplication of data in an edge network includes a compute device having circuitry to obtain a request to write a data set. The circuitry is also to apply, to the data set, an approximation function to produce an approximated data set. Additionally, the circuitry is to determine whether the approximated data set is already present in a shared memory and write, to a translation table and in response to a determination that the approximated data set is already present in the shared memory, an association between a local memory address and a location, in the shared memory, where the approximated data set is already present. Additionally, the circuitry is to increase a reference count associated with the location in the shared memory.

公开(公告)号：US20190097889A1

公开(公告)日：2019-03-28

申请号：US15716890

申请日：2017-09-27

Applicant: Intel Corporation

Inventor： John J. Browne ,  Timothy Verrall ,  Maryam Tahhan ,  Michael J. McGrath ,  Sean Harte ,  Kevin Devey ,  Jonathan Kenny ,  Christopher MacNamara

IPC: H04L12/24

Abstract: A computing apparatus, including: a hardware platform; and an interworking broker function (IBF) hosted on the hardware platform, the IBF including a translation driver (TD) associated with a legacy network appliance lacking native interoperability with an orchestrator, the IBF configured to: receive from the orchestrator a network function provisioning or configuration command for the legacy network appliance; operate the TD to translate the command to a format consumable by the legacy network appliance; and forward the command to the legacy network appliance.

公开(公告)号：US20190042617A1

公开(公告)日：2019-02-07

申请号：US15949097

申请日：2018-04-10

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Karthik Kumar ,  Mark Schmisseur ,  Timothy Verrall ,  Thomas Willhalm

IPC: G06F17/30

Abstract: Examples provide a network component, a network switch, a central office, a base station, a data storage element, a method, an apparatus, a computer program, a machine readable storage, and a machine readable medium. A network component (10) is configured to manage data consistency among two or more data storage elements (20, 30) in a network (40). The network component (10) comprises one or more interfaces (12) configured to register information on the two or more data storage elements (20, 30) comprising the data, information on a temporal range for the data consistency, and information on one or more address spaces at the two or more data storage elements (20, 30) to address the data. The network component (10) further comprises a logical component (14) configured to effect data updating at the two or more data storage elements (20, 30) based on the information on one or more address spaces at the two or more data storage elements (20, 30) and based on the information on the temporal range for the data consistency.