-
101.
公开(公告)号:BR122021025024A2
公开(公告)日:2022-03-15
申请号:BR122021025024
申请日:2020-05-20
Applicant: PANASONIC IP CORP AMERICA
Inventor: ABE KIYOFUMI , TOMA TADAMASA , NISHI TAKAHIRO , DRUGEON VIRGINIE , KATO YUSUKE
IPC: H04N19/70
Abstract: método de codificação, método de decodificação e mídia legível por computador não transitória. a presente invenção refere-se a um conjunto de circuitos (160) de um codificador (100) que é configurado para codificar uma imagem de acordo com uma estrutura de codificação, incluindo uma figura de ponto de acesso aleatório intra (irap), figura dianteiras a serem emitidas antes da figura de irap na ordem de emissão e figuras traseiras a serem emitidas após a figura de irap na ordem de emissão. quando a imagem é codificada, o conjunto de circuitos (160) codifica, de acordo com uma sinalização em um fluxo de bits, no máximo uma figura traseira entre as figuras traseiras antes de codificar as figuras dianteiras na ordem de codificação, e codifica as figuras traseiras diferentes de, no máximo, uma figura traseira após codificação das figuras dianteiras na ordem de codificação. a sinalização indica se uma imagem de cada uma das unidades de acesso no fluxo de bits é uma figura de campo. o conjunto de circuitos (160) codifica no máximo uma figura traseira antes de codificar as figuras dianteiras na ordem de codificação quando a sinalização indica que a figura é uma figura de campo.
-
公开(公告)号:SG11202112656UA
公开(公告)日:2021-12-30
申请号:SG11202112656U
申请日:2020-06-15
Applicant: PANASONIC IP CORP AMERICA
Inventor: TOMA TADAMASA , NISHI TAKAHIRO , ABE KIYOFUMI , KATO YUSUKE
IPC: H04N19/577
Abstract: An encoder (100) includes circuitry and memory connected to the circuitry. The circuitry, in operation: derives, as a first parameter, a total sum of absolute values of sums of horizontal gradient values respectively for pairs of relative pixel positions; derives, as a second parameter, a total sum of absolute values of sums of vertical gradient values respectively for the pairs of relative pixel positions; derives, as a third parameter, a total sum of horizontal-related pixel difference values respectively for the pairs of relative pixel positions; derives, as a fourth parameter, a total sum of vertical-related pixel difference values respectively for the pairs of relative pixel positions; derives, as a fifth parameter, a total sum of vertical-related sums of horizontal gradient values respectively for the pairs of relative pixel positions; and generates a prediction image to be used to encode the current block using the first, second, third, fourth, and fifth parameters.
-
公开(公告)号:SG11202111094YA
公开(公告)日:2021-11-29
申请号:SG11202111094Y
申请日:2020-04-16
Applicant: PANASONIC IP CORP AMERICA
Inventor: TOMA TADAMASA , NISHI TAKAHIRO , ABE KIYOFUMI , KATO YUSUKE
IPC: H04N19/159 , H04N19/12 , H04N19/176
Abstract: An encoder (100) includes: circuitry (160); and memory (162) coupled to the circuitry (160). In operation, the circuitry (160): derives a prediction error of the image by subtracting, from the image, a prediction image generated using intra prediction or inter prediction; performs primary transform on the prediction error, and performs secondary transform on a result of the primary transform; performs quantization on a result of the secondary transform; and encodes a result of the quantization as data of the image. In the performing of the secondary transform, when a matrix weighted intra prediction included in the intra prediction and having prediction modes is used, the circuitry (160) uses, as a transform set for the secondary transform, a common transform set shared among the prediction modes. The matrix weighted intra prediction generates the prediction image by performing matrix calculation on a pixel sequence obtained from pixel values of surrounding pixels of a current block, and the transform set for the secondary transform is applied to primary transform coefficients obtained from the result of the primary transform.
-
公开(公告)号:MX2021004194A
公开(公告)日:2021-05-27
申请号:MX2021004194
申请日:2019-12-06
Applicant: PANASONIC IP CORP AMERICA
Inventor: KATO YUSUKE , TOMA TADAMASA , NISHI TAKAHIRO , ABE KIYOFUMI
IPC: H04N19/70
Abstract: Un codificador (100) incluye la circuitería (160) y la memoria (162) acoplada a la circuitería (160), en la cual, en operación, la circuitería (160): divide una imagen actual para codificarla en dos o más mosaicos; codifica la imagen actual realizando la codificación sobre una base de rebanada, siendo la rebanada de forma rectangular y constituida por uno o más mosaicos o una parte de un mosaico obtenido por la división; y en la codificación de la imagen actual, excluye, de la información de encabezado, la información sobre una región ocupada por una rebanada ubicada en la esquina inferior derecha de la imagen actual.
-
公开(公告)号:CA3153767A1
公开(公告)日:2021-04-01
申请号:CA3153767
申请日:2020-07-03
Applicant: PANASONIC IP CORP AMERICA
Inventor: KATO YUSUKE , ABE KIYOFUMI , TOMA TADAMASA , NISHI TAKAHIRO
IPC: H04N19/13 , H04N19/157 , H04N19/18
Abstract: An encoding device (100) is provided with a circuit and a memory connected to the circuit, wherein the circuit, in operation, limits the number of times of processing of context adaptive encoding and encodes blocks of an image. In encoding of each of the blocks, in a case where the number of times of processing is in a limitation range of the number of times of processing, a coefficient information flag indicating an attribute of a coefficient included in the block is encoded. In encoding of the block, in a case where orthogonal transform is not applied to the block, when the coefficient information flag is encoded, transform processing is performed for transforming a coefficient value by using a value determined by using a peripheral coefficient that is a coefficient at the periphery of the position of a coefficient in the block, and the coefficient value after the transform processing is encoded by using the coefficient information flag encoded by the context adaptive encoding, whereas when the coefficient information flag is not encoded, the transform processing is not performed and the coefficient value is encoded by Golomb-Rice encoding.
-
公开(公告)号:SG11202100230PA
公开(公告)日:2021-02-25
申请号:SG11202100230P
申请日:2019-07-05
Applicant: PANASONIC IP CORP AMERICA
Inventor: LI JING YA , LIM CHONG SOON , SHASHIDHAR SUGHOSH PAVAN , LIAO RU LING , SUN HAI WEI , TEO HAN BOON , ABE KIYOFUMI , TOMA TADAMASA , NISHI TAKAHIRO
IPC: H04N19/52
Abstract: An encoder (100) includes circuitry (160) and memory (162) connected to the circuitry (160). In operation, the circuitry (160): selects a first table to be used for a current partition to be encoded in an image of a video, from among tables that are used to correct a base motion vector in a predetermined direction using a correction value specified by an index, the tables including correction values having varying differences between indexes; writes a parameter indicating a first index to be selected from among indexes included in the first table; and encodes the current partition using the base motion vector corrected using a correction value specified by the first index.
-
107.
公开(公告)号:MX2020013276A
公开(公告)日:2021-02-22
申请号:MX2020013276
申请日:2020-01-08
Applicant: PANASONIC IP CORP AMERICA
Inventor: TOMA TADAMASA , NISHI TAKAHIRO , OHKAWA MASATO , SAITOU HIDEO , ABE KIYOFUMI , KANOH RYUICHI
IPC: H04N19/12 , H04N19/124 , H04N19/157 , H04N19/176 , H04N19/18 , H04N19/625
Abstract: Se proporciona un codificador (100) que codifica un bloque actual en una imagen que incluye circuitaje y memoria. Usando la memoria, el circuitaje: realiza una primera transformada sobre una señal residual del bloque actual usando una base de primera transformada para generar coeficientes de primera transformada; y realiza una segunda transformada sobre los coeficientes de primera transformada usando una base de segunda transformada para generar coeficientes de segunda transformada y cuantificar los coeficientes de segunda transformada, cuando la base de primera transformada es la misma que una base de transformada predeterminada; y cuantifica los coeficientes de primera transformada sin realizar la segunda transformada cuando la base de primera transformada es diferente de la base de transformada predeterminada.
-
公开(公告)号:AU2019303651A1
公开(公告)日:2021-01-28
申请号:AU2019303651
申请日:2019-07-05
Applicant: PANASONIC IP CORP AMERICA
Inventor: LI JING YA , LIM CHONG SOON , SHASHIDHAR SUGHOSH PAVAN , LIAO RU LING , SUN HAI WEI , TEO HAN BOON , ABE KIYOFUMI , TOMA TADAMASA , NISHI TAKAHIRO
IPC: H04N19/52
Abstract: A coding device (100) is provided with a circuit (160) and a memory (162) connected to the circuit (160). The circuit (160): selects, from a plurality of tables which are used, during an operation, to correct a reference motion vector into a predetermined direction using a correction value designated by an index, and which have correction values with respectively different intervals between indexes, a first table used for a partition to be coded of an image in a moving image; writes a parameter indicating a first index to be selected from among indexes included in the first table; and codes the partition using the reference motion vector corrected by means of a correction value designated by the first index.
-
公开(公告)号:SG11202011403WA
公开(公告)日:2020-12-30
申请号:SG11202011403W
申请日:2019-05-09
Applicant: PANASONIC IP CORP AMERICA
Inventor: TOMA TADAMASA , NISHI TAKAHIRO , ABE KIYOFUMI , KANOH RYUICHI , LIM CHONG SOON , SHASHIDHAR SUGHOSH PAVAN , LIAO RU LING , SUN HAI WEI , TEO HAN BOON , LI JING YA
IPC: H04N19/119 , H04N19/176 , H04N19/70
Abstract: An encoder (100) partitions into blocks using a set of block partition modes obtained by combining one or more block partition modes defining a partition type. The set of block partition modes includes a first partition mode defining the partition direction and number of partitions for partitioning a first block, and a second block partition mode defining the partition direction and number of partitions for partitioning a second block which is one of blocks obtained after the first block is partitioned. When the number of partitions of the first block partition mode is three, the second block is a center block among the blocks obtained after partitioning the first block, and the partition direction of the second block partition mode is same as the partition direction of the first block partition mode, the second block partition mode includes only a block partition mode indicating that the number of partitions is three.
-
公开(公告)号:CA3135146A1
公开(公告)日:2020-10-22
申请号:CA3135146
申请日:2020-04-16
Applicant: PANASONIC IP CORP AMERICA
Inventor: TOMA TADAMASA
IPC: H04N19/12 , H04N19/159 , H04N19/176
Abstract: An encoding device derives, by subtracting, from an image, a prediction image of the image that is generated by an intra prediction or an inter prediction, an prediction error of the image (S311), performs primary transform on the prediction error (S312), performs secondary transform on the result of the primary transform (S312), performs quantization on the result of the secondary transform (S313), and encodes the result of the quantization as data of the image (S314). When performing the secondary transform, when a matrix computation type intra prediction (MIP) in which a prediction image is generated by performing a matrix computation on a pixel array obtained from pixel values of peripheral pixels of an object block and which has a plurality of prediction modes is used as the intra prediction, the encoding device uses a transform set common to the plurality of prediction modes as a transform set of the secondary transform that is applied for a primary transform coefficient obtained by the result of the primary transform (S312).
-
-
-
-
-
-
-
-
-