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公开(公告)号:KR20210008482A
公开(公告)日:2021-01-22
申请号:KR20207032454
申请日:2019-05-14
Applicant: PANASONIC IP CORP AMERICA
Inventor: LIM CHONG SOON , SUN HAI WEI , SHASHIDHAR SUGHOSH PAVAN , TEO HAN BOON , LIAO RU LING , LI JING YA , TOMA TADAMASA , NISHI TAKAHIRO , ABE KIYOFUMI , KANOH RYUICHI
IPC: H04N19/52 , H04N19/105 , H04N19/119 , H04N19/184 , H04N19/70
Abstract: 부호화장치(100)는, 회로(160)와, 메모리(162)를구비하고, 회로(160)는, 메모리(162)를이용하여, 제1 파티션의제1 움직임벡터에대한복수의후보를포함하는리스트이며, 당해리스트의최대리스트사이즈및 당해리스트에포함되는복수의후보의순서중 적어도한쪽이, 제1 파티션의파티션사이즈및 파티션형상중 적어도한쪽에의존하는리스트를생성하는단계와, 리스트에포함되는복수의후보중에서제1 움직임벡터를선택하는단계와, 최대리스트사이즈에의거하여, 리스트에포함되는복수의후보중 제1 움직임벡터를가리키는인덱스를비트스트림으로부호화하는단계와, 제1 움직임벡터를이용하여제1 파티션의예측화상을생성하는단계를행한다.
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公开(公告)号:KR20200139270A
公开(公告)日:2020-12-11
申请号:KR20207034738
申请日:2018-07-11
Applicant: PANASONIC IP CORP AMERICA
Inventor: OHKAWA MASATO , SAITOU HIDEO , TOMA TADAMASA , NISHI TAKAHIRO , ABE KIYOFUMI , KANOH RYUICHI
IPC: H04N19/625 , H04N19/124 , H04N19/176 , H04N19/18 , H04N19/423
Abstract: 픽처의부호화대상블록을부호화하는부호화장치(100)로서, 회로및 메모리를구비하고, 회로는메모리를이용하여, 제1 변환기저를이용하여부호화대상블록의잔차신호에제 1 변환을행함으로써제1 변환계수를생성하고, 제1 변환기저가소정변환기저와일치하는경우는, 제2 변환기저를이용하여제1 변환계수에제2 변환을행함으로써제2 변환계수를생성하고, 제2 변환계수를양자화하고, 제1 변환기저가소정변환기저와다른경우는, 제2 변환을행하지않고제1 변환계수를양자화한다.
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公开(公告)号:KR20200133813A
公开(公告)日:2020-11-30
申请号:KR20207032950
申请日:2019-05-09
Applicant: PANASONIC IP CORP AMERICA
Inventor: TOMA TADAMASA , NISHI TAKAHIRO , ABE KIYOFUMI , KANOH RYUICHI , LIM CHONG SOON , SHASHIDHAR SUGHOSH PAVAN , LIAO RU LING , SUN HAI WEI , TEO HAN BOON , LI JING YA
IPC: H04N19/119 , H04N19/176 , H04N19/42 , H04N19/70
Abstract: 요약서부호화장치(100)는, 분할타입을정의한블록분할모드를 1개또는복수조합한블록분할모드세트를이용하여복수의블록으로분할하고, 블록분할모드세트는, 제1 블록을분할하기위한분할방향과분할수를정의한제1 블록분할모드와, 제1 블록의분할후에얻어진블록중 하나인제2 블록을분할하기위한분할방향과분할수를정의한제2 블록분할모드로이루어지고, 제1 블록분할모드의분할수가 3이고, 제2 블록이, 제1 블록의분할후에얻어진블록중 중앙의블록이며, 또한, 제2 블록분할모드의분할방향이, 제1 블록분할모드의분할방향과같은경우, 제2 블록분할모드는분할수가 3인블록분할모드만을포함한다.
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公开(公告)号:WO2018123800A1
公开(公告)日:2018-07-05
申请号:PCT/JP2017045911
申请日:2017-12-21
Applicant: PANASONIC IP CORP AMERICA
Inventor: KANOH RYUICHI , NISHI TAKAHIRO , TOMA TADAMASA
IPC: H04N19/82 , H04N19/117 , H04N19/136
Abstract: An encoding device (100) that realizes further improvements is provided with a processing circuit and a memory. Using this memory, the processing circuit converts each of blocks, respectively comprising a plurality of pixels, into a block comprising a plurality of conversion coefficients using the base, reconstructs a block comprising the plurality of pixels by performing at least inverse conversion on each block comprising the plurality of conversion coefficients, determines filter characteristics for the boundary of two reconstructed blocks adjacent to each other on the basis of a combination of the bases used for the conversion of each of the two blocks (steps S1201, S1202), and performs a deblocking filter process having the determined filter characteristics (step S1203).
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公开(公告)号:MX2024004990A
公开(公告)日:2024-05-07
申请号:MX2024004990
申请日:2020-02-18
Applicant: PANASONIC IP CORP AMERICA
Inventor: LIM CHONG SOON , SUN HAI WEI , TOMA TADAMASA , NISHI TAKAHIRO , ABE KIYOFUMI , KANOH RYUICHI , SHASHIDHAR SUGHOSH PAVAN , TEO HAN BOON , LIAO RU LING , LI JING YA
IPC: H04N19/537 , H04N19/105 , H04N19/157 , H04N19/96
Abstract: Se proporciona un codificador de imagen el cual incluye conjunto de circuitos y una memoria acoplada al conjunto de circuitos. En operación, el conjunto de circuitos realiza: división de un bloque de imagen en una pluralidad de divisiones que incluyen una primera división que tiene una forma no rectangular (por ejemplo, una forma triangular) y una segunda división; predecir un primer vector de movimiento para la primera división y un segundo vector de movimiento para la segunda división; y codificar la primera división usando el primer vector de movimiento y la segunda división usando el segundo vector de movimiento.
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公开(公告)号:CA3100839C
公开(公告)日:2022-06-21
申请号:CA3100839
申请日:2019-05-09
Applicant: PANASONIC IP CORP AMERICA
Inventor: TOMA TADAMASA , NISHI TAKAHIRO , ABE KIYOFUMI , KANOH RYUICHI , LIM CHONG SOON , SHASHIDHAR SUGHOSH PAVAN , LIAO RU LING , SUN HAI WEI , TEO HAN BOON , LI JING YA
IPC: H04N19/119 , H04N19/176 , H04N19/70
Abstract: A coding device (100) performs division into a plurality of blocks by using a block division mode set obtained by combining one or more block division modes which define division types. The block division mode set comprises: a first block division mode in which the number of divisions and the dividing direction for dividing a first block are defined; and a second block division mode in which the number of divisions and the dividing direction for dividing a second block, which is one of blocks acquired by dividing the first block are defined. When a division in the first block mode results in three blocks, the second block is the center block among the blocks acquired by dividing the first block, and the dividing direction of the second block division mode is the same as the dividing direction of the first block division mode, then the second block division mode includes only a block division mode in which a division results in three blocks.
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公开(公告)号:AU2019274735A1
公开(公告)日:2020-12-10
申请号:AU2019274735
申请日:2019-05-09
Applicant: PANASONIC IP CORP AMERICA
Inventor: TOMA TADAMASA , NISHI TAKAHIRO , ABE KIYOFUMI , KANOH RYUICHI , LIM CHONG SOON , SHASHIDHAR SUGHOSH PAVAN , LIAO RU LING , SUN HAI WEI , TEO HAN BOON , LI JING YA
IPC: H04N19/119 , H04N19/176 , H04N19/70
Abstract: A coding device (100) performs division into a plurality of blocks by using a block division mode set obtained by combining one or more block division modes which define division types. The block division mode set comprises: a first block division mode in which the number of divisions and the dividing direction for dividing a first block are defined; and a second block division mode in which the number of divisions and the dividing direction for dividing a second block, which is one of blocks acquired by dividing the first block are defined. When a division in the first block mode results in three blocks, the second block is the center block among the blocks acquired by dividing the first block, and the dividing direction of the second block division mode is the same as the dividing direction of the first block division mode, then the second block division mode includes only a block division mode in which a division results in three blocks.
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公开(公告)号:CA3238600A1
公开(公告)日:2019-11-28
申请号:CA3238600
申请日:2019-05-09
Applicant: PANASONIC IP CORP AMERICA
Inventor: TOMA TADAMASA , NISHI TAKAHIRO , ABE KIYOFUMI , KANOH RYUICHI , LIM CHONG SOON , SHASHIDHAR SUGHOSH PAVAN , LIAO RU LING , SUN HAI WEI , TEO HAN BOON , LI JING YA
Abstract: An encoder partitions into blocks using a set of block partition modes obtained by combining one or more block partition modes defining a partition type. The set of block partition modes includes a first partition mode defining the partition direction and number of partitions for partitioning a first block, and a second block partition mode defining the partition direction and number of partitions for partitioning a second block which is one of blocks obtained after the first block is partitioned. When the number of partitions of the first block partition mode is three, the second block is a center block among the blocks obtained after partitioning the first block, and the partition direction of the second block partition mode is same as the partition direction of the first block partition mode, the second block partition mode includes only a block partition mode indicating that the number of partitions is three.
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公开(公告)号:CA3072997A1
公开(公告)日:2019-02-28
申请号:CA3072997
申请日:2018-08-10
Applicant: PANASONIC IP CORP AMERICA
Inventor: ABE KIYOFUMI , NISHI TAKAHIRO , TOMA TADAMASA , KANOH RYUICHI , LIM CHONG SOON , LIAO RU LING , SUN HAI WEI , SHASHIDHAR SUGHOSH PAVAN , TEO HAN BOON , LI JING YA
IPC: H04N19/117 , H04N19/157 , H04N19/80
Abstract: An image encoder is provided, which includes circuitry and a memory coupled to the circuitry. The circuitry, in operation, performs a boundary smoothing operation along a boundary between a first partition having a non-rectangular shape (e.g., a triangular shape) and a second partition that are split from an image block. The boundary smoothing operation includes: first-predicting first values of a set of pixels of the first partition along the boundary, using information of the first partition; second-predicting second values of the set of pixels of the first partition along the boundary, using information of the second partition; weighting the first values and the second values; and encoding the first partition using the weighted first values and the weighted second values.
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公开(公告)号:PL3691273T3
公开(公告)日:2025-03-31
申请号:PL18862113
申请日:2018-09-20
Applicant: PANASONIC IP CORP AMERICA
Inventor: ABE KIYOFUMI , NISHI TAKAHIRO , TOMA TADAMASA , KANOH RYUICHI , HASHIMOTO TAKASHI
IPC: H04N19/52 , H04N19/105 , H04N19/146 , H04N19/156 , H04N19/167 , H04N19/436 , H04N19/53 , H04N19/533
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