公开(公告)号：JPS56130898A

公开(公告)日：1981-10-14

申请号：JP3513480

申请日：1980-03-19

Applicant: SONY CORP

Inventor： TSUCHIYA TAKAHISA ,  SONEDA MITSUO ,  NAKAMURA ISA ,  TOKUHARA MASAHARU ,  KITA HIROYUKI

IPC: G11C27/04 ,  G11C19/18 ,  H01L21/339 ,  H01L21/822 ,  H01L27/04 ,  H01L29/762 ,  H03H11/26 ,  H03H15/02 ,  H04N5/30

Abstract: PURPOSE:To prevent the decrease in the dynamic range with a simple constitution, by selecting the coefficient of split of capacitor forming BBD so that the specified conditions can be satisfied and the DC level of the 1st and 2nd BBDs connected each other is made in agreement. CONSTITUTION:Capacitors C0' ,C0'', C1', C1'', C4', C4'', C5', C5''... forming BBDa split with coefficients a0, a1, a4, a5...' and the capacitors Cb0' and Cb0'' of BBDb connected to BBDa via the connection circuit 9 are split with the coefficient b. When the coefficients a0...'b are selected so that the conditions of equation I can be satisfied, the DC level on and after the capacitor Cb2 of BBDb to which the output of BBDa is fed is corrected and the DC level of BDDa and BBDb is in agreement. Thus, with a simple constitution, the decrease in the dynamic range can be prevented and no signal deterioration like waveform distortion can not be generated.

公开(公告)号：JPS56124197A

公开(公告)日：1981-09-29

申请号：JP2842280

申请日：1980-03-06

Applicant: SONY CORP

Inventor： TSUCHIYA TAKAHISA ,  SONEDA MITSUO

IPC: G11C19/18 ,  G11C27/04 ,  H01L21/339 ,  H01L29/762 ,  H04N5/335 ,  H04N5/372 ,  H04N5/374 ,  H04N5/376

Abstract: PURPOSE:To reduce power consumption with a simple constitution, by controlling the constant-current source, which drives the output stage, through two sets of switching transistors which are operated according to the oscillation output which drives a differential circuit. CONSTITUTION:The differential circuit formed with transistors 11 and 12 and so on is driven by oscillation source 100 to control transistors 17 and 21 through constant-current source 16 of constant current I0. At the same time, switching transistors 31 and 32, whose emitters connected commonly are connected to constant-current source 33 of constant current I1, are turned on and off alternately according to the output of oscillation source 100, and NPN and PNP transistors 19, 20, 23, and 24 of the output stage are controlled to switch the connection to power source terminal side 4 and the earth side, and the charge transfer element connected to terminals 6 and 7 is driven. By this constitution, the current consumption of the circuit except transistors 19, 20, 23, and 24 becomes I0+I1, and thus, the driving circuit is obtained which has the current consumption lower than I0+2I1 of the circuit not provided with switching transistors.

公开(公告)号：JPS56122286A

公开(公告)日：1981-09-25

申请号：JP2555180

申请日：1980-02-29

Applicant: SONY CORP

Inventor： TSUCHIYA TAKAHISA ,  SONEDA MITSUO

IPC: H03H15/02 ,  H04N9/78

Abstract: PURPOSE:To form all circuits on one chip of an IC, by constituting a filter, which separates a luminance signal and a chroma signal, with a transversal filter using a charge transfer element. CONSTITUTION:The composite color video signal from input terminal 1 is supplied to delay circuits DX1-DX2 constituting the charge transfer element such as a BBD. The signal from terminal 1 and outputs of circuits DX1-DX4 are supplied to synthesizer A1 through weighting circuits X0-X8. The signal of synthesizer A1 is supplied to delay circuits DZ1-DZ10 constituting the BBD, and outputs of circuits DZ1-DZ4 are supplied to synthesizer A1 through Z3, Z51, Z7 and Z9 to eliminate the sound signal. Outputs of circuits DZ1-DZ11 are supplied to supplied to synthesizer A2 through weighting circuits Z2-Z22 to separate the chroma signal. Further, outputs of circuits DZ6, DZ8, DZ10 and DZ12 are supplied to synthesizer A3 through weighting circuits Z12, Z15, Z19 and Z24 to delay luminance signal by a desired quantity and separate it.

公开(公告)号：JPS5693182A

公开(公告)日：1981-07-28

申请号：JP16864179

申请日：1979-12-25

Applicant: SONY CORP

Inventor： SONEDA MITSUO

IPC: G11C27/04 ,  G11C27/00

Abstract: PURPOSE:To realize a process of a high-frequency signal with a simple constitution, by driving the BBD with several types of clock signals. CONSTITUTION:An input signal of the terminal 1 has a 50% duty cycle and then supplied to four parallel BBDs which are driven by the 1st clock signal having two phases opposite to each other. THe phase is shifted by 360 deg./4=90 deg. for the 1st clock signal supplied to each BBD. And both the input and output stages of each BBD are driven by the 2nd clock signal having a time duration corresponding to 90 deg.. Thus the output signals are obtained successively at the terminal 11. As a result, the signal of a high frequency is processed with a low clock frequency.

公开(公告)号：JPS5687296A

公开(公告)日：1981-07-15

申请号：JP16532879

申请日：1979-12-18

Applicant: SONY CORP

Inventor： TSUCHIYA TAKAHISA ,  SONEDA MITSUO ,  NAKAMURA ISA ,  KITA HIROYUKI ,  TOKUHARA MASAHARU

IPC: H03H15/02 ,  G11C27/00 ,  G11C27/04 ,  H03H15/00

Abstract: PURPOSE:To simplify the circuit constitution and obtain an output having a good property, by extracting the signals obtained from the adjacent capacities in the different clock signal periods and then holding the peak value of the extracted signal to obtain an output. CONSTITUTION:With supply of clock pulses phi1 and phi2 to BBD, a high signal is extracted at the connection point of the emitters of transistors 31 and 32. This signal is supplied to the capacitor 38 through the transistors 33 and 36. The transistor 36 is turned on at the signal part of the signal which is supplied to the base of the transistor 36, and this potential is held. At the same time, the transistor 36 receives an adverse bias at the high potential part. The signal held is delivered to the output terminal 41 through the transistor 39.

公开(公告)号：JPS5683113A

公开(公告)日：1981-07-07

申请号：JP16008479

申请日：1979-12-10

Applicant: SONY CORP

Inventor： TSUCHIYA TAKAHISA ,  SONEDA MITSUO

IPC: H03H15/02 ,  H03K5/003

Abstract: PURPOSE:To enable DC level shift with a simple constitution, by DC correction through the difference of each DC component between the quantity of charge injected to a capacitor at feedback point and the quantity of charge flowing to a transistor at feedback point. CONSTITUTION:An input terminal 1 is connected to the base of pnp transistor TR2, the collector of TR2 is connected to the power supply terminal 4 and the emitter is grounded via the constant current source 3. The emitter of TR2 is connected to one end of a capacitor CON via a diode 5 of opposite connection and connected to a capacitor CIN via TRQ1. Taking the capacitance value of capacitors CON, CIN at the prestage from the capacitor 2 at feedback point as CN, DC correction can be made by determining the value of CN through the differnce of the DC components (QT), (QR), which are the DC components of the quantity of QT flowing to TRQ2 and the quantity of charge QR injected to the capacitor C2. Thus, DC level shift is made with a simple constitution.

公开(公告)号：JPS5661092A

公开(公告)日：1981-05-26

申请号：JP13656379

申请日：1979-10-22

Applicant: SONY CORP

Inventor： TSUCHIYA TAKAHISA ,  SONEDA MITSUO

IPC: G11C27/04 ,  G11C27/00 ,  H01L21/339 ,  H01L29/76 ,  H01L29/762

Abstract: PURPOSE:To correct the DC level shift with a simple constitution, by superimposing DC component on the input signal of BBD and the charge of active element driven with the signal in-phase with the transfer clock on the current output. CONSTITUTION:A signal component 51 and a DC component 53 are fed to BBD via a terminal 1, and the current output is picked up through a capacitive element from an arbitrary stage. Further, the DC component corresponding to the DC component 53 is fed to charge transfer elements 21-25, the signal phi1' in phase with transfer clocks phi1, phi2 is commonly fed to each control terminal of a pair of complemental active elements 11, 12 and 16, 17, the controlled terminals of the active elements are commonly connected, and a capacitor 25 and a capacitive element at an arbitrary stage are connected to the connecting point. Further, the charge flowing to the active element 16 is superimposed on the current output, the capacitive value of an arbitrary stage of capacitive element and the capacitor 25 is respectively determined to an arbitrary value, and the DC potential of the current output can arbitrarily be corrected.

公开(公告)号：JPS5661091A

公开(公告)日：1981-05-26

申请号：JP13656279

申请日：1979-10-22

Applicant: SONY CORP

Inventor： TSUCHIYA TAKAHISA ,  SONEDA MITSUO

IPC: G11C27/04 ,  G11C27/00 ,  H01L21/339 ,  H01L29/762 ,  H01L29/78

Abstract: PURPOSE:To perform the DC level shift correction with a simple constitution, by superimposing DC component on the input signal of BBD and DC output of charge transfer element provided separately on the current output. CONSTITUTION:A signal component 51 and a DC component 53 are fed to BBD via a terminal 1, it is sequentially transferred in synchronizing with clocks phi1, phi2 from a drive device 8 and picked up as current output through a capacitive element from an arbitrary stage. Further, a DC component corresponding to the DC component 53 is fed to charge transfer elements 21-25, the charge flowing to the active element 25 at the final stage is superimposed on the DC output, and the capacitance value of the capacitive element on an arbitrary stage of BBD and the capacitor 24 can respectively be determined to an arbitrary value. Thus, the DC potential of current output can arbitrarily be corrected.

公开(公告)号：JPS55145370A

公开(公告)日：1980-11-12

申请号：JP5308979

申请日：1979-04-27

Applicant: SONY CORP

Inventor： TSUCHIYA TAKAHISA ,  SONEDA MITSUO

IPC: G11C27/04 ,  H01L21/339 ,  H01L29/762 ,  H01L29/768

Abstract: PURPOSE:To eliminate the fluctuation of a DC potential in an output circuit of a charge transfer element by connecting the cold end side of any capacity of the element to a pair of complementary active elements, supplying a clock signal to the active element and connecting a capacitive element thereto. CONSTITUTION:Signals equivalent to signals phi2 varying at VDC and VDC+VP are supplied to the cold end side of a capacitor C2n. A capacitor C2n-1 is charged by the discharge of the capacitor C2n and the base current of a transistor Q2n. The discharge of the capacitor C2n is executed by supplying charge from a capacitor 15 through a transistor 11 conducting by the signal phi1 of the same phase as the signal phi1 as reverse phase to the signal phi2. At this time charge is also supplied form the capacitor 15 to the capacitor 10. When comparing the final charge amount of the capacitor 15 with the charge amount of the capacitor C0 at initial stage when supplying the signal thereto, the charge amounts in the DC components are coincident.

公开(公告)号：JPS5597098A

公开(公告)日：1980-07-23

申请号：JP497979

申请日：1979-01-19

Applicant: SONY CORP

Inventor： TSUCHIYA TAKAHISA ,  SONEDA MITSUO

IPC: G11C11/56 ,  G11C11/34 ,  G11C19/28 ,  G11C27/00 ,  G11C27/04 ,  H01L21/339 ,  H01L29/762 ,  H01L29/78 ,  H03H7/30 ,  H03H15/02

Abstract: PURPOSE:To obtain the good output by giving the weighting to the delay signal obtained from the intermediate tap such as BBD or the like and also eliminating the DC level shift. CONSTITUTION:The terminal potential of capacitor C0' varies in the period during which clock signal phi1 features the fixed potential immediately after the input signal is supplied to terminal 1. Meanwhile the charge is discharged via the collector of complementary transistor TR11, and the charge of C2' is discharged in the period during which signal phi1 features the fixed potential for next one clock period tau. The charge amount discharged from the collector of TR11 features the same phase as signal phi1 and then turns into the addition signal which is weighted with signal phi1' featuring the fixed potential. In that case, signal phi1' is charged to C43 for the prescribed period of signal phi1, and the charge equivalent to the charging charge gives charging to C32 via current Miller circuit 44. As a result, the DC level shift is eliminated for the discharged current given from TR11, thus obtaining the desired output voltage at terminal 33.