公开(公告)号：KR1020170118682A

公开(公告)日：2017-10-25

申请号：KR1020177012332

申请日：2015-10-20

Applicant: 헤드웨이 테크놀로지스 인코포레이티드

Inventor： 무어테리 ,  니스브란트

IPC: B24B37/013 ,  B24B49/12 ,  H01L21/302 ,  H01L21/3105 ,  H01L21/321 ,  H01L21/66 ,  B81C99/00

CPC classification number: B24B37/013 ,  B24B49/12 ,  B81C99/0065 ,  B81C2201/0104 ,  H01L21/302 ,  H01L21/31053 ,  H01L21/3212 ,  H01L22/12 ,  H01L22/26

Abstract: 적응형피드백제어방법은기판상의두 개의환형영역들사이의유전체층세정시간차를최소화하기위해화학적기계적연마공정을위해제공된다. 광학윈도우를갖는광학시스템은연마패드아래로통과하고적어도 2 개의환형영역들로부터반사광간섭신호들을검출한다. 사전-세정시간차이가결정되어 CMP 헤드막 압력및 리테이닝링 압력중 하나또는둘 모두에대한조정을계산하는데 사용된다. 압력조정은제 2 연마주기의필요성을피하고적어도 2 개의환형영역들내의금속층의디싱차이및 저항차를감소시키기위해연마주기의종료전에적용된다. 몇몇실시예들에서, 제 2 압력조정은주기의종료전에수행되고상이한 CMP 헤드막 압력조정들이상이한압력구역들에서헹헤진다.

Abstract translation: 提供了一种自适应反馈控制方法用于化学机械抛光工艺，以最小化衬底上两个环形区域之间的电介质层清洁时间差。 具有光学窗口的光学系统通过抛光垫下方并检测来自至少两个环形区域的反射光干涉信号。 确定预清洁时间差并用于计算对CMP头膜片压力和保持环压力中的一个或两个的调节。 在抛光周期结束之前施加压力调整以避免需要第二抛光周期并且减少至少两个环形区域中的凹陷差异和金属层的电阻差异。 在一些实施例中，在循环结束之前执行第二压力调整，并且在不同的压力区域中冲洗不同的CMP头膜压力调整。

公开(公告)号：KR1020120025585A

公开(公告)日：2012-03-15

申请号：KR1020127000269

申请日：2010-05-27

Applicant: 바스프 에스이

Inventor： 장지후아 ,  달비바이브하브 ,  메히타비르다르바르 ,  페치텐쾨터안드레아스 ,  리유주오 ,  로테르미카엘

IPC: C09K3/14

CPC classification number: C09G1/02 ,  C01B33/18 ,  C01F17/0043 ,  C01P2004/03 ,  C01P2004/32 ,  C01P2004/62 ,  C01P2004/64 ,  C01P2004/84 ,  C09C3/063 ,  C09K3/1436 ,  C09K3/1445 ,  C09K3/1463 ,  C23C16/02 ,  H01L21/30625 ,  H01L21/31053 ,  B81C2201/0104

Abstract: Si, Ti, Zr, Al, Zn의 금속 산화물 및 이의 혼합물로 이루어진 군에서 선택되고 크기가 20 내지 100 nm이 코어를 포함하고, 상기 코어는 입자 크기가 10 nm 이하인 CeCo
2 입자로 코팅된 것인 라스베리형 코팅 입자; i) Si, Ti, Zr, Al, Zn의 금속 산화물 및 이의 혼합물로 이루어진 군에서 선택되고, 입자 크기가 20 내지 100 nm인 코어 입자; b) 수용성 Ce-염, 및 c) 물을 함유하는 혼합물을 제공하는 단계; ii) 10 내지 90℃의 온도에서 유기 또는 무기 염기를 i) 단계의 혼합물에 부가하는 단계, 및 iii) 10 내지 90℃의 온도에서 혼합물을 숙성시키는 단계를 포함하는 라스베리형 코팅 입자의 제조 방법; 및 상기 입자를 함유하는 폴리싱제 및 표면 폴리싱용으로서 이들의 용도에 관한 것이다.

公开(公告)号：US20180201503A1

公开(公告)日：2018-07-19

申请号：US15923013

申请日：2018-03-16

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Michael T. Brigham ,  Christopher V. Jahnes ,  Cameron E. Luce ,  Jeffrey C. Maling ,  William J. Murphy ,  Anthony K. Stamper ,  Eric J. White

IPC: B81C1/00 ,  G06F17/50 ,  B81B3/00

CPC classification number: B81C1/0015 ,  B81B3/0021 ,  B81B2203/0118 ,  B81B2203/0315 ,  B81B2207/09 ,  B81C1/00047 ,  B81C1/00269 ,  B81C1/00365 ,  B81C1/00531 ,  B81C1/00936 ,  B81C2201/0104 ,  B81C2201/0107 ,  B81C2201/0121 ,  B81C2201/0125 ,  B81C2201/0132 ,  B81C2201/0176 ,  B81C2201/0181 ,  B81C2203/0109 ,  B81C2203/0145 ,  B81C2203/0714 ,  G06F17/5009

Abstract: Micro-Electro-Mechanical System (MEMS) structures, methods of manufacture and design structures are disclosed. The method includes forming a Micro-Electro-Mechanical System (MEMS) beam structure by venting both tungsten material and silicon material above and below the MEMS beam to form an upper cavity above the MEMS beam and a lower cavity structure below the MEMS beam.

公开(公告)号：US20180201502A1

公开(公告)日：2018-07-19

申请号：US15916962

申请日：2018-03-09

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Michael T. Brigham ,  Christopher V. Jahnes ,  Cameron E. Luce ,  Jeffrey C. Maling ,  William J. Murphy ,  Anthony K. Stamper ,  Eric J. White

IPC: B81C1/00 ,  G06F17/50 ,  B81B3/00

CPC classification number: B81C1/0015 ,  B81B3/0021 ,  B81B2203/0118 ,  B81B2203/0315 ,  B81B2207/09 ,  B81C1/00047 ,  B81C1/00269 ,  B81C1/00365 ,  B81C1/00531 ,  B81C1/00936 ,  B81C2201/0104 ,  B81C2201/0107 ,  B81C2201/0121 ,  B81C2201/0125 ,  B81C2201/0132 ,  B81C2201/0176 ,  B81C2201/0181 ,  B81C2203/0109 ,  B81C2203/0145 ,  B81C2203/0714 ,  G06F17/5009

Abstract: Micro-Electro-Mechanical System (MEMS) structures, methods of manufacture and design structures are disclosed. The method includes forming a Micro-Electro-Mechanical System (MEMS) beam structure by venting both metal material and silicon material above and below the MEMS beam to form an upper cavity above the MEMS beam and a lower cavity structure below the MEMS beam.

公开(公告)号：US09981842B2

公开(公告)日：2018-05-29

申请号：US15162988

申请日：2016-05-24

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Michael T. Brigham ,  Christopher V. Jahnes ,  Cameron E. Luce ,  Jeffrey C. Maling ,  William J. Murphy ,  Anthony K. Stamper ,  Eric J. White

IPC: B81C1/00 ,  G06F17/50 ,  B81B3/00

CPC classification number: B81C1/0015 ,  B81B3/0021 ,  B81B2203/0118 ,  B81B2203/0315 ,  B81B2207/09 ,  B81C1/00047 ,  B81C1/00269 ,  B81C1/00365 ,  B81C1/00531 ,  B81C1/00936 ,  B81C2201/0104 ,  B81C2201/0107 ,  B81C2201/0121 ,  B81C2201/0125 ,  B81C2201/0132 ,  B81C2201/0176 ,  B81C2201/0181 ,  B81C2203/0109 ,  B81C2203/0145 ,  B81C2203/0714 ,  G06F17/5009

Abstract: Micro-Electro-Mechanical System (MEMS) structures, methods of manufacture and design structures are disclosed. The method includes forming a Micro-Electro-Mechanical System (MEMS) beam structure by venting both tungsten material and silicon material above and below the MEMS beam to form an upper cavity above the MEMS beam and a lower cavity structure below the MEMS beam.

公开(公告)号：US09914118B2

公开(公告)日：2018-03-13

申请号：US14824518

申请日：2015-08-12

Applicant: International Business Machines Corporation

Inventor： Yann A. Astier ,  Markus Brink ,  Michael F. Lofaro ,  Joshua T. Smith

IPC: G01N27/447 ,  B01L3/00 ,  G01N33/487 ,  B81C1/00 ,  B24B37/04 ,  G01N30/74 ,  G01N30/60 ,  G01N30/88

CPC classification number: B01L3/502707 ,  B01L3/502753 ,  B01L3/502761 ,  B01L2200/0652 ,  B01L2200/12 ,  B01L2300/0681 ,  B01L2300/0858 ,  B01L2300/0887 ,  B01L2300/0896 ,  B24B37/042 ,  B81C1/00087 ,  B81C2201/0104 ,  B81C2201/013 ,  G01N27/44791 ,  G01N30/6039 ,  G01N30/74 ,  G01N33/48721 ,  G01N2030/885

Abstract: A technique relates to a nanogap array. A substrate has been anisotropically etched with trenches that have tapered sidewalls. A sacrificial layer is on bottoms and the tapered sidewalls of the trenches. A filling material is formed on top of the sacrificial layer in the trenches. Nanogaps are formed where at least a portion of the sacrificial layer has been removed from the tapered sidewalls of the trenches while the sacrificial layer remains on the bottoms of the trenches. Each of the nanogaps is formed between one tapered sidewall of the substrate and a corresponding tapered sidewall of the filling material. The one tapered sidewall of the substrate opposes the corresponding tapered sidewall. A capping layer is disposed on top of the substrate and the filling material, such that the nanogaps are covered but not filled in.

公开(公告)号：US09873137B2

公开(公告)日：2018-01-23

申请号：US14799632

申请日：2015-07-15

Applicant: HITACHI, LTD.

Inventor： Shuntaro Machida ,  Takashi Kobayashi

IPC: B06B1/02 ,  B81C1/00 ,  C09K13/00 ,  H01L21/306 ,  C23F4/00 ,  H01L29/84

CPC classification number: B06B1/0292 ,  B81C1/00158 ,  B81C1/00182 ,  B81C1/00214 ,  B81C1/00476 ,  B81C1/00531 ,  B81C1/00611 ,  B81C2201/0104 ,  B81C2201/0107 ,  B81C2201/0109 ,  C09K13/00 ,  C23F4/00 ,  H01L21/30604 ,  H01L29/84 ,  Y10T29/49156

Abstract: Disclosed is an ultrasonic transducer that is provided with: a bottom electrode; an electric connection part which is connected to the bottom electrode from the bottom of the bottom electrode; a first insulating film which is formed so as to cover the bottom electrode; a cavity which is formed on the first insulating film so as to overlap the bottom electrode when seen from above; a second insulating film which is formed so as to cover the cavity; and a top electrode which is formed on the second insulating film so as to overlap the cavity when seen from above. The electric connection part to the bottom electrode is positioned so as to not overlap the cavity when seen from above.

公开(公告)号：US09862600B2

公开(公告)日：2018-01-09

申请号：US14718152

申请日：2015-05-21

Applicant: ams International AG

Inventor： Roel Daamen ,  Hendrik Bouman ,  Kailash Vijayakumar

IPC: B81C1/00 ,  H01L23/64 ,  B81B7/00

CPC classification number: B81C1/00825 ,  B81B7/0016 ,  B81B2201/0264 ,  B81B2203/0127 ,  B81B2207/015 ,  B81B2207/03 ,  B81C2201/0104 ,  B81C2201/0146 ,  B81C2203/0735 ,  H01L23/642

Abstract: One example discloses an chip, comprising: a substrate; a first side of a passivation layer coupled to the substrate; a device, having a device height and a cavity, wherein a first device surface is coupled to a second side of the passivation layer which is opposite to the first side of the passivation layer; and a set of structures coupled to the second side of the passivation layer and configured to have a structure height greater than or equal to the device height.

公开(公告)号：US09782773B2

公开(公告)日：2017-10-10

申请号：US14950320

申请日：2015-11-24

Applicant: International Business Machines Corporation

Inventor： Yann A. Astier ,  Markus Brink ,  Michael F. Lofaro ,  Joshua T. Smith

IPC: H01L21/311 ,  B01L3/00 ,  B81C1/00 ,  B24B37/04 ,  G01N27/447 ,  G01N33/487 ,  G01N30/74 ,  G01N30/60 ,  G01N30/88

CPC classification number: B01L3/502707 ,  B01L3/502753 ,  B01L3/502761 ,  B01L2200/0652 ,  B01L2200/12 ,  B01L2300/0681 ,  B01L2300/0858 ,  B01L2300/0887 ,  B01L2300/0896 ,  B24B37/042 ,  B81C1/00087 ,  B81C2201/0104 ,  B81C2201/013 ,  G01N27/44791 ,  G01N30/6039 ,  G01N30/74 ,  G01N33/48721 ,  G01N2030/885

Abstract: A technique relates to a nanogap array. A substrate has been anisotropically etched with trenches that have tapered sidewalls. A sacrificial layer is on bottoms and the tapered sidewalls of the trenches. A filling material is formed on top of the sacrificial layer in the trenches. Nanogaps are formed where at least a portion of the sacrificial layer has been removed from the tapered sidewalls of the trenches while the sacrificial layer remains on the bottoms of the trenches. Each of the nanogaps is formed between one tapered sidewall of the substrate and a corresponding tapered sidewall of the filling material. The one tapered sidewall of the substrate opposes the corresponding tapered sidewall. A capping layer is disposed on top of the substrate and the filling material, such that the nanogaps are covered but not filled in.

公开(公告)号：US09714473B2

公开(公告)日：2017-07-25

申请号：US14191061

申请日：2014-02-26

Applicant: Microfabrica Inc.

Inventor： Uri Frodis ,  Adam L. Cohen ,  Michael S. Lockard

IPC: C25D5/02 ,  C25D5/10 ,  C25D5/48 ,  B33Y10/00 ,  B81C1/00 ,  B81C99/00 ,  C25D1/00 ,  C25D21/12 ,  H01L21/288 ,  H01L21/768

CPC classification number: C25D5/48 ,  B33Y10/00 ,  B81C1/00492 ,  B81C99/0065 ,  B81C2201/0104 ,  B81C2201/0197 ,  C25D1/00 ,  C25D1/003 ,  C25D5/022 ,  C25D5/10 ,  C25D21/12 ,  H01L21/2885 ,  H01L21/76885 ,  Y10T156/1052

Abstract: Some embodiments of the present invention provide processes and apparatus for electrochemically fabricating multilayer structures (e.g. mesoscale or microscale structures) with improved endpoint detection and parallelism maintenance for materials (e.g. layers) that are planarized during the electrochemical fabrication process. Some methods involve the use of a fixture during planarization that ensures that planarized planes of material are parallel to other deposited planes within a given tolerance. Some methods involve the use of an endpoint detection fixture that ensures precise heights of deposited materials relative to an initial surface of a substrate, relative to a first deposited layer, or relative to some other layer formed during the fabrication process. In some embodiments planarization may occur via lapping while other embodiments may use a diamond fly cutting machine.