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    DATA SHIFTING
    103.
    发明公开
    DATA SHIFTING 审中-公开
    数据移位

    公开(公告)号：EP3047485A1

    公开(公告)日：2016-07-27

    申请号：EP14846610.5

    申请日：2014-08-28

    Applicant: Micron Technology, Inc.

    Inventor： COWLES, Timothy B. ,  BODILY, Steven M.

    IPC: G11C7/10 ,  G11C7/06

    CPC classification number: G11C7/065 ,  G11C5/06 ,  G11C7/06 ,  G11C7/08 ,  G11C7/1006 ,  G11C7/1036 ,  G11C7/22 ,  G11C8/10 ,  G11C11/4091 ,  G11C19/00 ,  G11C2207/002 ,  G11C2207/005

    Abstract: The present disclosure includes apparatuses and methods related to data shifting. An example apparatus comprises a first memory cell coupled to a first sense line of an array, a first isolation device located between the first memory cell and first sensing circuitry corresponding thereto, and a second isolation device located between the first memory cell and second sensing circuitry corresponding to a second sense line. The first and the second isolation devices are operated to shift data in the array without transferring the data via an input/output line of the array.

    Abstract translation: 本公开包括与数据移位有关的设备和方法。 示例装置包括耦合到阵列的第一感测线的第一存储器单元，位于第一存储器单元和与其对应的第一感测电路之间的第一隔离器件以及位于第一存储器单元和第二感测电路之间的第二隔离器件 对应于第二感测线。 操作第一和第二隔离装置以移位阵列中的数据而不通过阵列的输入/输出线传送数据。

    ADJUSTING A DIGITAL DELAY FUNCTION OF A DATA MEMORY UNIT
    105.
    发明授权
    ADJUSTING A DIGITAL DELAY FUNCTION OF A DATA MEMORY UNIT 有权
    调整数字延迟功能的数据存储单元的

    公开(公告)号：EP1997112B1

    公开(公告)日：2011-03-02

    申请号：EP06725144.7

    申请日：2006-03-17

    Applicant: Telefonaktiebolaget LM Ericsson (publ)

    Inventor： RUTHEMANN, Klaus

    IPC: G11C29/02 ,  G11C7/10 ,  G11C8/06

    CPC classification number: G11C7/1036 ,  G11C7/22 ,  G11C7/222 ,  G11C8/06 ,  G11C29/003 ,  G11C29/02

    Abstract: An apparatus for adjustment of a digital delay function of a data memory unit comprising said data memory unit (102), an elastic store register, ESR, (104) and read clock and write clock adapted to control read and write operations, a write counter associated with the write clock and a read counter associated with the read clock. Said memory (102) works in series with said ESR (104). The memory (102) delivers two data elements from two logically neighbouring cells. Said ESR (104) writes the two data elements from the memory (102) at every cycle of the write clock, wherein if the write counter is increased by one at a cycle of the write clock the output position in the memory (102) is not changed, and if the write counter is increased by two at one cycle of the write clock the output position in the memory (102) is moved backward by one data element and if the write counter is not changed at one cycle of the write clock the output position in the memory (102) is moved forward by one data element.

    FLEXIBLE AND AREA EFFICIENT COLUMN REDUNDANCY FOR NON-VOLATILE MEMORIES
    107.
    发明公开
    FLEXIBLE AND AREA EFFICIENT COLUMN REDUNDANCY FOR NON-VOLATILE MEMORIES 审中-公开
    灵活和节省面积列冗余非易失性存储器

    公开(公告)号：EP1700314A1

    公开(公告)日：2006-09-13

    申请号：EP04815107.0

    申请日：2004-12-20

    Applicant: SanDisk Corporation

    Inventor： CERNEA, Raul-Adrian ,  LI, Yan

    IPC: G11C29/00

    CPC classification number: G11C7/1036 ,  G11C29/848

    Abstract: The present invention presents a non-volatile memory wherein bad columns in the array of memory cells can be removed. According to another aspect of the present invention, substitute redundant columns can replace the removed columns. Both of these processes are performed on the memory in a manner that is externally transparent and, consequently, need not be managed externally by the host or controller to which the memory is attached. An inventory of the bad columns can be maintained on the memory. At power up, the list of bad columns is used to fuse out the bad columns. The memory may also contain a number of redundant columns that can be used to replace the bad columns.

    METHODS AND APPARATUS FOR IMPROVED MEMORY ACCESS
    108.
    发明公开
    METHODS AND APPARATUS FOR IMPROVED MEMORY ACCESS 有权
    方法和提高内存器件

    公开(公告)号：EP1576445A2

    公开(公告)日：2005-09-21

    申请号：EP03810796.7

    申请日：2003-10-23

    Applicant: Ring Technology Entreprises, LLC

    Inventor： LYNCH, William, T. ,  HERBISON, David, J.

    IPC: G06F1/00

    CPC classification number: G11C29/32 ,  G06F13/1673 ,  G11C7/1036 ,  G11C29/12 ,  G11C29/1201 ,  G11C2029/3202

    Abstract: A memory access scheme employing one or more sets of shift registers interconnected in series to which data may be loaded from or written into one or more memory devices. That is, data from the memory devices may be parallel loaded into the sets of shift registers and then serially shifted through the shift registers until it is output from the sets of shift registers and transferred to its destination. Additionally, the data may be read from and loaded into the memory devices to/from the sets of shift registers such that the shifting of the shift registers is uninterrupted during the reading and/or loading of data. Additionally, data from the memory devices may be loaded into two or more parallel chains of shift registers and then serially shifted through the shift register chains.

    Memory expansion circuit
    109.
    发明公开
    Memory expansion circuit 审中-公开
    电路，用于存储器扩展

    公开(公告)号：EP1288956A3

    公开(公告)日：2003-08-06

    申请号：EP02023417.5

    申请日：1999-02-10

    Applicant: Lexmark International, Inc.

    Inventor： Gibson, Bruce David ,  Parish, George Keith

    IPC: G11C8/00 ,  G11C7/10 ,  G11C8/10

    CPC classification number: B41J2/17546 ,  B41J2/04541 ,  B41J2/04563 ,  B41J2/0458 ,  B41J2/17526 ,  B41J25/34 ,  B41J2202/17 ,  G11C7/1036 ,  G11C8/10

    Abstract: A memory device for storing and outputting information includes a plurality of memory matrices, each memory matrix containing a plurality of transistors having a drain, a source, and a gate and the plurality of transistors are arranged in a plurality of levels that proceed from a lowest to a highest level. A plurality of single bit shift registers is also provided for producing a serial output, each shift register having a memory input and an associated memory matrix, wherein the memory input of each shift register is electrically connected to the sources of the transistors in the highest level of the shift register's associated memory matrix. A plurality of address lines for receiving a decode signal function, a load signal, and a clock as well as an output line for transmitting the serial output of the plurality of shift registers is also provided. Embodiments of the invention may employ any number of shift registers and memory matrices independent of the number of available address lines.

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