公开(公告)号：AT239255T

公开(公告)日：2003-05-15

申请号：AT98965007

申请日：1998-12-29

Applicant: MICRON TECHNOLOGY INC

Inventor： KLEIN DEAN A

IPC: G06F13/14 ,  G06F13/12 ,  G06F13/10 ,  G06F9/46 ,  G06F13/24

Abstract: A computer system maintains and updates a status register (102, 107) in response to signals containing status information received from several peripheral devices (110, 120, 130), and generates an interrupt to a processor (100). When the processor (100) sevices the interrupt, the processor (100) merely reads the status register (102) to determine which peripheral device requires processing. This is a very fast operation because the status register (102) is internal to the processor (100) or core logic (103). No time consuming polling of peripheral devices (110, 120, 130) is required to determine the status of the peripheral device.

公开(公告)号：WO2006019624A3

公开(公告)日：2009-04-16

申请号：PCT/US2005024322

申请日：2005-07-07

Applicant: MICRON TECHNOLOGY INC ,  KLEIN DEAN A

Inventor： KLEIN DEAN A

IPC: G11C7/00

CPC classification number: G11C11/406 ,  G11C7/1006 ,  G11C11/40622 ,  G11C2207/104 ,  G11C2211/4061 ,  G11C2211/4062 ,  G11C2211/4068

Abstract: A DRAM includes a register storing subsets of row addresses corresponding to rows containing at least one memory cell that is unable to store a data bit during a normal refresh cycle. Each subset includes all but the most significant bit of a corresponding row address. A refresh counter in the DRAM generates refresh row addresses that are used to refresh rows of memory cells. The refresh row addresses are compared to the subsets of row addresses that are stored in the register. In the event of a match, the row of memory cells corresponding to the matching subset of bits is refreshed. The number of refreshes occurring each refresh cycle will depend upon the number of bits in the subset that are omitted from the row address. The memory cells that are unable to retain data bits are identified by a modified sense amplifier.

Abstract translation: DRAM包括寄存器，存储对应于在正常刷新周期期间不能存储数据位的至少一个存储单元的行对应的行地址。 每个子集包括相应行地址的除最高有效位之外的所有子集。 DRAM中的刷新计数器产生用于刷新存储单元行的刷新行地址。 将刷新行地址与存储在寄存器中的行地址的子集进行比较。 在匹配的情况下，对应于匹配的比特子集的存储器单元行被刷新。 每个刷新周期中刷新的次数将取决于从行地址中省略的子集中的位数。 不能保留数据位的存储单元由修改的读出放大器识别。

公开(公告)号：US6438687B2

公开(公告)日：2002-08-20

申请号：US93206801

申请日：2001-08-17

Applicant: MICRON TECHNOLOGY INC

Inventor： KLEIN DEAN A

IPC: G06F9/445 ,  G06F11/20 ,  G06F9/06

CPC classification number: G06F11/1666 ,  G06F9/4401 ,  G06F11/20

Abstract: A computer system and method is described for improved storage of computer system configuration information. A ROM module includes both a BIOS ROM portion and a configuration ROM portion. The configuration ROM includes a backup copy of the system configuration parameters stored in a battery-powered configuration CMOS RAM. If the configuration CMOS RAM fails to provide valid configuration data, the contents of the configuration ROM are used to configure the computer system. If the contents of the configuration ROM are also invalid, default configuration values are provided by the BIOS ROM. User modification of the default values may be effected through a setup utility program, and the configuration ROM then programmed accordingly.

Abstract translation: 描述了用于改进计算机系统配置信息的存储的计算机系统和方法。 ROM模块包括BIOS ROM部分和配置ROM部分。 配置ROM包括存储在电池供电的配置CMOS RAM中的系统配置参数的备份副本。 如果配置CMOS RAM无法提供有效的配置数据，则配置ROM的内容将用于配置计算机系统。 如果配置ROM的内容也无效，BIOS ROM提供默认配置值。 默认值的用户修改可以通过设置实用程序来实现，然后配置ROM被相应地编程。

公开(公告)号：EP2875432A4

公开(公告)日：2016-03-23

申请号：EP13819365

申请日：2013-07-09

Applicant: MICRON TECHNOLOGY INC

Inventor： KLEIN DEAN A

IPC: G06F12/10 ,  G06F12/12

CPC classification number: G06F12/1009 ,  G06F3/0604 ,  G06F3/0647 ,  G06F3/0653 ,  G06F3/0685 ,  G06F12/1027 ,  G06F12/123 ,  G06F2212/1008 ,  G06F2212/657

Abstract: Disclosed are systems and methods for managing memory. A memory management system may include a table having multiple virtual memory addresses. Each virtual memory address may correspond to a physical memory address and data that identifies a type of memory device corresponding to the physical memory address. The physical memory device can be used to access the memory device when a table hit occurs.

公开(公告)号：EP2126919A4

公开(公告)日：2010-12-22

申请号：EP07865361

申请日：2007-12-07

Applicant: MICRON TECHNOLOGY INC

Inventor： KLEIN DEAN A

IPC: G11C11/00 ,  G06F12/02

CPC classification number: G11B7/14 ,  G06F12/0246 ,  G06F13/1673 ,  G06F13/1684 ,  Y02D10/13 ,  Y02D10/14

Abstract: A processor-based system includes a processor coupled to core logic through a processor bus. This includes a dynamic random access memory (“DRAM”) memory buffer controller. The DRAM memory buffer controller is coupled through a memory bus to a plurality of a dynamic random access memory (“DRAM”) modules and a flash memory module, which are at the same hierarchical level from the processor. Each of the DRAM modules includes a memory buffer to the memory bus and to a plurality of dynamic random access memory devices. The flash memory module includes a flash memory buffer coupled to the memory bus and to at least one flash memory device. The flash memory buffer includes a DRAM-to-flash memory converter operable to convert the DRAM memory requests to flash memory requests, which are then applied to the flash memory device.

公开(公告)号：EP3243137A4

公开(公告)日：2018-08-01

申请号：EP16735388

申请日：2016-01-07

Applicant: MICRON TECHNOLOGY INC

Inventor： WHEELER KYLE B ,  MURPHY RICHARD C ,  MANNING TROY A ,  KLEIN DEAN A

IPC: G06F12/02 ,  G06F9/30 ,  G06F9/38 ,  G06F15/78 ,  G11C7/06 ,  G11C7/10

CPC classification number: G06F9/3877 ,  G06F15/7821 ,  G11C7/06 ,  G11C7/065 ,  G11C7/1006 ,  G11C7/1036 ,  G11C11/4087 ,  G11C11/4096

Abstract: Examples of the present disclosure provide apparatuses and methods related to generating and executing a control flow. An example apparatus can include a first device configured to generate control flow instructions, and a second device including an array of memory cells, an execution unit to execute the control flow instructions, and a controller configured to control an execution of the control flow instructions on data stored in the array.

公开(公告)号：EP1119814A4

公开(公告)日：2001-09-26

申请号：EP98965007

申请日：1998-12-29

Applicant: MICRON TECHNOLOGY INC

Inventor： KLEIN DEAN A

IPC: G06F13/14 ,  G06F13/12 ,  G06F13/10 ,  G06F9/46 ,  G06F13/24

CPC classification number: G06F13/126

Abstract: A computer system maintains and updates a status register (102, 107) in response to signals containing status information received from several peripheral devices (110, 120, 130), and generates an interrupt to a processor (100). When the processor (100) sevices the interrupt, the processor (100) merely reads the status register (102) to determine which peripheral device requires processing. This is a very fast operation because the status register (102) is internal to the processor (100) or core logic (103). No time consuming polling of peripheral devices (110, 120, 130) is required to determine the status of the peripheral device.