Abstract:
There are provided a thin gold alloy wire for semiconductor chip bonding which is extremely useful in reducing the size of a semiconductor device and attaining a higher density, as well as a method for manufacturing the same. The thin gold alloy wire essentially consists of the invention's predetermined amounts of elements selected from Pt, Pd, Be, Ge, Ca, La, Y and Eu and the balance being Au and incidental impurity and has an elongation of 3% to 8% and a Young's modulus of 6,800 to 9,000 kgf/mm 2 . Since the thin wire is high in strength in spite of a small diameter, the occurrence of wire breaking during wiring and use is diminished and the deterioration of bonding strength after standing at a high temperature is reduced, so it is possible to suppress the breaking of the wire under vibration. By cooling a molten gold alloy 1 of the composition according to the invention within a crucible from the lower end toward the upper end of the crucible it is made possible to obtain positively and relatively easily a thin gold alloy wire having the aforesaid alloy composition and having an elongation of 3% to 8% and a Young's modulus of 6,800 to 9,000 kgf/mm 2 .
Abstract:
A corrosion tolerant bonding pad for a semiconductor device includes an interconnect (12) formed on the substrate (10) of the semiconductor device, a passivating layer (16) provided on the interconnect, the passivating layer having an aperture for exposing an enlarged bonding region of the interconnect, a barrier layer (28) provided on the exposed enlarged bonding area of the interconnect (12) and on portions of the passivating layer (16) surrounding the bonding area, and a bonding layer (30) provided on the barrier layer (28). The barrier layer is a non-corrosive, conductive material, for example, a compound of titanium and tungsten (TiW -- known as ti-tungsten).
Abstract:
Bonding wire for semiconductor device use where both leaning failures and spring failures are suppressed by (1) in a cross-section containing the wire center and parallel to the wire longitudinal direction (wire center cross-section), there are no crystal grains with a ratio a/b of a long axis "a" and a short axis "b" of 10 or more and with an area of 15 µm 2 or more ("fiber texture"), (2) when measuring a crystal direction in the wire longitudinal direction in the wire center cross-section, the ratio of crystal direction with an angle difference with respect to the wire longitudinal direction of 15° or less is, by area ratio, 50% to 90%, and (3) when measuring a crystal direction in the wire longitudinal direction at the wire surface, the ratio of crystal direction with an angle difference with respect to the wire longitudinal direction of 15° or less is, by area ratio, 50% to 90%. During the drawing steep, a drawing operation with a rate of reduction of area of 15.5% or more is performed at least once. The final heat treatment temperature and the pre-final heat treatment temperature are made predetermined ranges.
Abstract:
Bonding wire for semiconductor device use where both leaning failures and spring failures are suppressed by (1) in a cross-section containing the wire center and parallel to the wire longitudinal direction (wire center cross-section), there are no crystal grains with a ratio a/b of a long axis "a" and a short axis "b" of 10 or more and with an area of 15 µm 2 or more ("fiber texture"), (2) when measuring a crystal direction in the wire longitudinal direction in the wire center cross-section, the ratio of crystal direction with an angle difference with respect to the wire longitudinal direction of 15° or less is, by area ratio, 10% to less than 50%, and (3) when measuring a crystal direction in the wire longitudinal direction at the wire surface, the ratio of crystal direction with an angle difference with respect to the wire longitudinal direction of 15° or less is, by area ratio, 70% or more. During the drawing step, a drawing operation with a rate of reduction of area of 15.5% or more is performed at least once. The final heat treatment temperature and the pre-final heat treatment temperature are made predetermined ranges.
Abstract:
The present invention relates to a method of bonding a copper wire to a substrate, particularly a printed circuit board and an IC-substrate, possessing a layer assembly comprising a copper bonding portion and a palladium or palladium alloy layer and a substrate having a copper wire bonded to aforementioned layer assembly.
Abstract:
[Issues to be solved] Second bonding failures caused attached oxide of additive elements on high purity Au bonding wire are to be dissolved. [Solution means] Au alloy bonding wires comprising: 5 - 100 wt ppm Mg, 5 - 20 wt ppm In, 5 - 20 wt ppm Al, 5 - 20 wt ppm Yb, and Au residual is more than 99.995 wt % purity, and adding 5 - 20 wt ppm Ca, and for these alloys adding at least more than one element among 5 - 20 wt ppm La, 5 - 20 wt ppm Lu, 5 - 100 wt ppm Sn, 5 - 100 wt ppm Sr to the alloy, and/or, more over, adding 0.01 - 1.2 wt % Pd to these alloys. Bonding wire, which contains these trace additive elements .do not cause of disturbance by accumulated contamination, because of contamination, which formed at ball formation by micro discharge and at the first bonding to attached on tip of capillary, transferring to the wire at second bonding.
Abstract:
Die Erfindung beschreibt eine leistungselektronische Verbindungseinrichtung mit einer ersten (120) und einer zweiten (220) voneinander elektrisch isolierten Kontaktfläche, mit jeweils mindestens einem einer Edelmetalloberfläche (160,260) aufweisenden Kontaktbereich (16,26) auf diesen Kontaktflächen, je einer auf den Kontaktbereichen angeordneten Sintermetallschicht (18,28) und einem flexiblen Verbindungselement (4). Hierbei weist dieses Verbindungselement eigene dritte (40) und vierte (42) Kontaktbereiche mit jeweils einer Edelmetalloberfläche auf. Ebenso sind diese dritten und vierten Kontaktbereiche mit den Sintermetallschichten der ersten und zweiten Kontaktflächen elektrisch leitend verbunden. Die erste Kontaktfläche (120) kann auf einer Metallisierung (14) eines Substrats angeordnet sein une die zweite Kontaktfläche (220) kann auf einem Leistungshalbleiterbauelement (1) angeordnet sein.
Abstract:
A ball-bond arrangement comprising an aluminum bond pad of a semiconductor device and a wire ball-bonded to the aluminum bond pad, wherein the wire has a diameter of 10 to 80 pm and comprises a core consisting of a copper alloy consisting of 0.05 to 3 wt.-% of palladium and/or platinum with copper as the remainder to make up 100 wt.-%.