公开(公告)号：WO2008007121A1

公开(公告)日：2008-01-17

申请号：PCT/GB2007/002652

申请日：2007-07-13

Applicant: WOLFSON MICROELECTRONICS PLC ,  STEELE, Colin ,  HEARNE, Catherine, Ann ,  SINGLETON, David, Paul

Inventor： STEELE, Colin ,  HEARNE, Catherine, Ann ,  SINGLETON, David, Paul

IPC: H05B33/08 ,  H04N1/48

CPC classification number: H05B33/089 ,  H04N1/40056 ,  H04N1/484 ,  H05B33/0818 ,  H05B33/0857 ,  Y02B20/347

Abstract: A driver apparatus is provided for controlling a light source array comprising at least first and second light sources, the light source array used for illuminating a scan region on a target object, wherein light reflected from said target object is captured by a detector. The driver apparatus comprises a single integrated circuit comprising processing means for processing image data received from the detector, a switching array comprising at least first and second switches for switching the respective first and second light sources, and a current source for controlling the flow of current through the light sources. In this way the LED switching circuitry that controls an LED array is placed on the same integrated circuit (i.e. monolithic circuit) as the analogue processing circuitry that processes the image data, with the current source controlling the flow of current through the LEDs in the LED array. The current source has the advantage of avoiding rapid changes or slope discontinuities in the current flowing through the LEDs, which would otherwise cause unwanted transient signals. A shunt path comprising a switching device may be provided in parallel with the LED array and switching array. The shunt path has the advantage of enabling the switching sequence from one LED to another to be controlled such that a substantially constant current is drained from the supply (subject to any differences in the inherent current drawn by the Red, Green and Blue LEDs, respectively).

Abstract translation: 提供一种用于控制包括至少第一和第二光源的光源阵列的驱动器装置，所述光源阵列用于照射目标物体上的扫描区域，其中由所述目标物体反射的光被检测器捕获。 驱动器装置包括单个集成电路，其包括用于处理从检测器接收的图像数据的处理装置，包括用于切换相应的第一和第二光源的至少第一和第二开关的开关阵列，以及用于控制电流流动的电流源 通过光源。 以这种方式，控制LED阵列的LED开关电路放置在与处理图像数据的模拟处理电路相同的集成电路（即，单片电路）上，电流源控制通过LED中的LED的电流 阵列。 电流源具有避免流过LED的电流的快速变化或斜率不连续性的优点，否则将导致不期望的瞬态信号。 包括开关装置的并联路径可以与LED阵列和开关阵列并联设置。 分流路径具有使得能够控制从一个LED到另一个LED的切换序列的优点，使得从电源中排出基本上恒定的电流（经受由红色，绿色和蓝色LED分别绘制的固有电流的任何差异 ）。

公开(公告)号：WO2007020404A1

公开(公告)日：2007-02-22

申请号：PCT/GB2006/003014

申请日：2006-08-11

Applicant: WOLFSON MICROELECTRONICS PLC ,  MAGRATH, Anthony, James ,  WESTLAKE, John

Inventor： MAGRATH, Anthony, James ,  WESTLAKE, John

IPC: H03F3/217 ,  H03F1/34 ,  H03F1/32 ,  H03F3/30

CPC classification number: H03F3/30 ,  H03F1/32 ,  H03F1/3217 ,  H03F1/34 ,  H03F3/217 ,  H03F3/2173 ,  H03F2200/351 ,  H03F2200/78

Abstract: A feedback controller in a PWM amplifier comprises a signal input for receiving a pulse width modulated (PWM) input signal (Vin) whose duty cycle represents a desired analogue output signal. A feedback loop filter (518) generates a filtered error signal (Vint) comprising a filtered representation of differences between the input signal (Vin) and a feedback signal (Vfb). A comparator (520) compares the filtered error signal with a reference to generate a provisional PWM switching control signal (C) for controlling the PWM amplifier (500). A pulse conditioner (532) receives both the provisional PWM switching control signal (C) and the PWM input signal (X=Vin) and outputs to the amplifier (500) a conditioned PWM switching control signal (Y), modified in accordance with predetermined constraints in relation to the PWM input signal.

Abstract translation: PWM放大器中的反馈控制器包括用于接收其占空比表示期望的模拟输出信号的脉宽调制（PWM）输入信号（Vin）的信号输入。 反馈环路滤波器（518）产生包括输入信号（Vin）和反馈信号（Vfb）之间的差分的滤波表示的滤波误差信号（Vint）。 比较器（520）将滤波的误差信号与基准进行比较，以产生用于控制PWM放大器（500）的临时PWM切换控制信号（C）。 脉冲调节器（532）同时接收临时PWM切换控制信号（C）和PWM输入信号（X = Vin），并且向放大器（500）输出经调节的PWM切换控制信号（Y），根据预定的PWM切换控制信号 与PWM输入信号有关的约束。

公开(公告)号：WO2014064421A1

公开(公告)日：2014-05-01

申请号：PCT/GB2013/052640

申请日：2013-10-10

Applicant: WOLFSON MICROELECTRONICS PLC

Inventor： LESSO, John Paul

IPC: H03M3/00

CPC classification number: H04R3/00 ,  H03M1/66 ,  H03M3/374 ,  H03M3/50

Abstract: This application relates to digital-to-analogue conversion with improved noise performance. Embodiments relate to digital-to-analogue conversion circuits (300 ) for converting a digital audio signal to an analogue audio signal having a digital-to- analogue converter(104) operable at a plurality of DAC clock rates. A first clock controller (301-1) controls the DAC clock rate based on an indication of the amplitude of the audio signal. The DAC clock rate (CK 1 ) may be increased for low amplitude signal, where noise is important, to reduce the in-band thermal noise of the DAC. At higher amplitudes, when noise is less audible, the DAC clock rate may be reduced to avoid distortion. The amplitude of the audio signal may be monitored by a digital level detector (302) or in some cases by an analogue level detector (303). The DAC may be an oversampling DAC with an input interpolator (101) The conversion circuit may also include a word-length reduction module (102) and a dynamic error matching module (103) whose clock rates may also be varied based on the signal.

Abstract translation: 该应用涉及具有改进的噪声性能的数模转换。 实施例涉及用于将数字音频信号转换为模拟音频信号的数模转换电路（300），模拟音频信号具有可以多个DAC时钟速率工作的数模转换器（104）。 第一时钟控制器（301-1）基于音频信号的幅度的指示来控制DAC时钟速率。 对于噪声很重要的低幅度信号，DAC时钟频率（CK1）可能会增加，以降低DAC的带内热噪声。 在较高的幅度下，当噪声较小时，DAC时钟频率可能会降低，以避免失真。 音频信号的幅度可以由数字电平检测器（302）监视，或者在某些情况下由模拟电平检测器（303）监视。 DAC可以是具有输入内插器的过采样DAC（101）。转换电路还可以包括字长减小模块（102）和动态误差匹配模块（103），其时钟速率也可以基于该信号而变化。

公开(公告)号：WO2014060723A1

公开(公告)日：2014-04-24

申请号：PCT/GB2013/052641

申请日：2013-10-10

Applicant: WOLFSON MICROELECTRONICS PLC

Inventor： LESSO, John Paul

IPC: H03M1/06 ,  H03M1/70

CPC classification number: H03G3/001 ,  H03M1/0624 ,  H03M1/0626 ,  H03M1/0863 ,  H03M1/66 ,  H03M1/70

Abstract: The application relates to digital to analogue conversion circuits having dynamic gain control. A digital variable gain element (102) may apply gain to an input digital signal (D IN ) upstream of a DAC (101) to make better use of the input range of the DAC and an analogue variable gain element (103) applies a compensating analogue gain. Again controller (201) has a gain allocation module (204) for controlling the allocation of gain between said digital and analogue variable gain elements in response to changes in a signal level of the input digital audio signal. In the present invention the gain allocation module is operable in first and second modes of operation where the response to reductions in signal level is slower in the first mode than in the second mode of operation. A low-level detector (202) monitors the input digital audio signal so as to detect a low-level part of the signal and the gain controller changes from the first mode to the second mode following detection o fa low-level part of the input digital audio signal. The response of the gain allocation module in the second mode is preferably fast enough such that the digital gain can be changed to a target setting suitable for the low-level part of the signal before it is received at the digital gain element.

Abstract translation: 该应用涉及具有动态增益控制的数模转换电路。 数字可变增益元件（102）可以对DAC（101）上游的输入数字信号（DIN）施加增益，以更好地利用DAC的输入范围，并且模拟可变增益元件（103）应用补偿模拟 获得。 再次，控制器（201）具有增益分配模块（204），用于响应于输入数字音频信号的信号电平的变化来控制所述数字和模拟可变增益元件之间的增益分配。 在本发明中，增益分配模块可在第一和第二操作模式中操作，其中对第一模式的信号电平降低的响应比在第二操作模式中更慢。 低电平检测器（202）监视输入数字音频信号，以便检测信号的低电平部分，并且增益控制器在检测到输入的低电平部分之后从第一模式改变到第二模式 数字音频信号。 增益分配模块在第二模式中的响应优选地足够快，使得数字增益可以在其在数字增益元件被接收之前被改变为适合于信号的低电平部分的目标设置。

公开(公告)号：WO2014045041A1

公开(公告)日：2014-03-27

申请号：PCT/GB2013/052459

申请日：2013-09-19

Applicant: WOLFSON MICROELECTRONICS PLC

Inventor： HOEKSTRA, Tsjerk ,  JENKINS, Colin Robert

IPC: H04R19/00

CPC classification number: H04R1/08 ,  B81B3/0021 ,  B81B2201/0257 ,  B81C1/00158 ,  H04R19/005 ,  H04R2201/003

Abstract: This application relates to MEMS devices, especially MEMS capacitive transducers and to processes for forming such MEMS transducer that provide increased robustness and resilience to acoustic shock. The application describes a MEMS transducer (400) having at least one membrane layer (101) supported so as to define a flexible membrane. A strengthening layer (401; 701) is mechanically coupled to the membrane layer and is disposed around the majority of a peripheral area of the flexible membrane but does not extend over the whole flexible membrane. The strengthening layer, which in some embodiments may be formed from the same material as the membrane electrode (102) being disposed in the peripheral area helps reduce stress in membrane at locations that otherwise may be highly stressed in acoustic shock situations. The membrane may be supported over a substrate cavity and the strengthening layer may be provided in an area of the membrane that could make contact with the edge (202) of the substrate cavity.

Abstract translation: 本申请涉及MEMS器件，特别是MEMS电容式换能器，以及用于形成这样的MEMS换能器的方法，其提供对声学冲击的增强的鲁棒性和弹性。 该应用描述了具有至少一个膜层（101）被支撑以限定柔性膜的MEMS换能器（400）。 加强层（401; 701）机械耦合到膜层并且围绕柔性膜的周边区域的大部分设置，但不延伸遍布整个柔性膜。 在一些实施例中，加强层可以由与设置在周边区域中的膜电极（102）相同的材料形成，有助于在声学冲击情况下可能会受到高应力的位置减小膜中的应力。 膜可以被支撑在衬底空腔上，并且加强层可以设置在可以与衬底腔的边缘（202）接触的膜的区域中。

公开(公告)号：WO2013088173A1

公开(公告)日：2013-06-20

申请号：PCT/GB2012/053151

申请日：2012-12-14

Applicant: WOLFSON MICROELECTRONICS PLC

Inventor： LESSO, John Paul ,  FRITH, Peter John ,  PENNOCK, John Laurence

IPC: H04L25/49

CPC classification number: G10L19/167 ,  G10L19/002 ,  H04L25/49 ,  H04L25/4902 ,  H04L25/4904

Abstract: This application relates to methods and apparatus for transfer of multiple digital data streams, especially of digital audio data over a single communications link such as a single wire. The application describes audio interface circuitry comprising a pulse- length-modulation(PLM) modulator (204). The PLM is responsive to a plurality of data streams (PDM-R, PDM-L), to generate a seriesof data pulses (PLM)with a single data pulse having a rising and falling edge in each of a plurality of transfer periods defined by a first clock signal (TCLK). The timing of the rising and falling edgeof each data pulse is dependent upon on a combination of the then current data samples from the plurality of data streams. The duration and position of the data pulse in the transfer window in effect defines a data symbol encoding the data. Circuitry for receiving and extracting the data is also disclosed. An interface receives the stream of data pulses (PLM) and data extraction circuitry (202) samplesthe data pulseto determine which of the possible data symbols the pulse representsand determines a data value for at least one received data stream.

Abstract translation: 本申请涉及用于通过单个通信链路（例如单线）传送多个数字数据流，特别是数字音频数据的方法和装置。 应用描述了包括脉冲长度调制（PLM）调制器（204）的音频接口电路。 PLM响应于多个数据流（PDM-R，PDM-L），以产生一系列数据脉冲（PLM），其中单个数据脉冲具有由多个传输周期中的每一个定义的上升沿和下降沿 第一时钟信号（TCLK）。 每个数据脉冲的上升沿和下降沿的定时取决于来自多个数据流的当前当前数据样本的组合。 传输窗口中的数据脉冲的持续时间和位置有效地定义了对数据进行编码的数据符号。 还公开了用于接收和提取数据的电路。 接口接收数据脉冲流（PLM）和数据提取电路（202），对数据脉冲进行采样，以确定脉冲表示哪些可能数据符号，并确定至少一个接收到的数据流的数据值。

公开(公告)号：WO2012085598A3

公开(公告)日：2012-11-15

申请号：PCT/GB2011052580

申请日：2011-12-23

Applicant: WOLFSON MICROELECTRONICS PLC ,  LESSO JOHN PAUL ,  FRITH PETER JOHN ,  PENNOCK JOHN LAURENCE

Inventor： LESSO JOHN PAUL ,  FRITH PETER JOHN ,  PENNOCK JOHN LAURENCE

IPC: H02M3/07 ,  H02M1/00

CPC classification number: H02M3/07 ,  H02M1/00 ,  H02M2001/0083 ,  H02M2001/009 ,  H03F3/181

Abstract: A bipolar output charge pump circuit 100 is provided having a network of switching paths 110 for selectively connecting an input node (VV) and a reference node (VG) for connection to an input voltage, a first pair of output nodes (VP, VN) and a second pair of output nodes (VQ, VM), and two pairs of flying capacitor nodes (CF1A, CF1B; CF2A, CF2B), and a controller for controlling the switching of the network of switching paths. The controller is operable to control the network of switching paths when in use with two flying capacitors (CF1, CF2) connected to the two pairs of flying capacitor nodes, to provide a first bipolar output voltage at the first pair of output nodes (VP, VN) and a second bipolar output voltage at the second pair of bipolar output nodes (VQ, VM).

Abstract translation: 提供双极性输出电荷泵电路100，其具有用于选择性地连接用于连接到输入电压的输入节点（VV）和参考节点（VG）的开关路径110的网络，第一对输出节点（VP，VN） 以及第二对输出节点（VQ，VM）和两对飞行电容器节点（CF1A，CF1B; CF2A，CF2B）和用于控制交换路径网络的切换的控制器。 控制器可操作以在与两对飞跨电容器节点连接的两个飞行电容器（CF1，CF2）使用时控制开关路径网络，以在第一对输出节点（VP， VN）和在第二对双极输出节点（VQ，VM）处的第二双极性输出电压。

公开(公告)号：WO2012076900A1

公开(公告)日：2012-06-14

申请号：PCT/GB2011/052444

申请日：2011-12-09

Applicant: WOLFSON MICROELECTRONICS PLC ,  LLEWELLYN, Steven ,  WEIL, Richard

Inventor： LLEWELLYN, Steven ,  WEIL, Richard

IPC: H04R1/10

CPC classification number: H04R1/1083 ,  G10K11/178 ,  H04R3/00 ,  H04R2460/01

Abstract: An earphone has a casing, containing a speaker, the casing being adapted to fit within the outer ear of a user at the entrance to the ear canal of the user. The casing has a guide, protruding from the front surface of the casing, and suitable for locating in the ear canal of the user. The casing is also adapted to allow sound to pass through a sound-permeable portion of the front surface. The casing has sound channels, leading across the front surface of the casing from the sound-permeable portion to a periphery of the first surface of the casing. The earphone can be used in a noise cancelling earphone system, with signal processing circuitry connected to the microphone and to the speaker, wherein the signal processing circuitry is adapted to receive the ambient noise signal from the microphone, and to apply the ambient noise signal to a filter having a controllable amount of gain, for generating a noise cancellation signal for transmission to the speaker. The result is that, however the earphone is worn within the outer ear of a user, an amount of sound leakage lies within a predetermined range, such that the amount of gain to be applied by the signal processing circuitry falls within a relatively narrow range.

Abstract translation: 耳机具有容纳扬声器的壳体，所述壳体适于在使用者的耳道的入口处装配在使用者的外耳内。 壳体具有从壳体的前表面突出并且适于定位在使用者的耳道中的引导件。 壳体还适于允许声音通过前表面的透声部分。 壳体具有通道，从壳体的前表面从透声部分引导到壳体的第一表面的周边。 耳机可用于降噪耳机系统中，信号处理电路连接到麦克风和扬声器，其中信号处理电路适于从麦克风接收环境噪声信号，并将环境噪声信号施加到 具有可控增益量的滤波器，用于产生用于传输到扬声器的噪声消除信号。 结果是，耳机佩戴在用户的外耳内，声音泄漏量在预定范围内，使得由信号处理电路施加的增益量落在相对窄的范围内。

公开(公告)号：WO2011073681A1

公开(公告)日：2011-06-23

申请号：PCT/GB2010/052137

申请日：2010-12-17

Applicant: WOLFSON MICROELECTRONICS PLC ,  HATFIELD, Robert, James ,  MCLEOD, Gordon, Richard ,  PENNOCK, John, Laurence

Inventor： HATFIELD, Robert, James ,  MCLEOD, Gordon, Richard ,  PENNOCK, John, Laurence

IPC: G06F13/42

CPC classification number: G06F13/4291 ,  G06F1/04 ,  G06F1/12 ,  G06F13/00 ,  G06F13/4282 ,  H04J3/00 ,  H04J3/16 ,  Y02D10/14 ,  Y02D10/151

Abstract: The present invention relates to methods and apparatus for data transfer. A data interface is described with at least a first data terminal for either outputting or receiving a data signal. In bi-directional embodiments there may be one terminal for receiving data and one terminal for outputting data. A bit clock terminal outputs or receives a bit clock signal; and a frame clock terminal for outputs or receives a frame clock signal. Interface control circuitry is configurable to associate data outputted or received in each frame with time slots (1-8) of a predetermined number of bits (x, y, z) wherein the control circuitry is adapted such that the frequency of the bit clock signal can be changed at any time so as to vary the number of time slots in a frame.

Abstract translation: 本发明涉及用于数据传送的方法和装置。 至少使用数据接口描述用于输出或接收数据信号的第一数据终端。 在双向实施例中，可以存在用于接收数据的一个终端和用于输出数据的一个终端。 位时钟端子输出或接收位时钟信号; 以及用于输出或接收帧时钟信号的帧时钟终端。 接口控制电路可配置为将每帧中输出或接收的数据与预定位数（x，y，z）的时隙（1-8）相关联，其中控制电路适于使得位时钟信号 可以随时更改，以便改变帧中的时隙数。

公开(公告)号：WO2011010146A3

公开(公告)日：2011-03-17

申请号：PCT/GB2010051193

申请日：2010-07-20

Applicant: WOLFSON MICROELECTRONICS PLC ,  HAIPLIK HOLGER ,  GRAEFJE DIETER

Inventor： HAIPLIK HOLGER ,  GRAEFJE DIETER

IPC: G06F1/14 ,  G06F1/30 ,  H03K3/012

CPC classification number: G06F1/14 ,  G06F1/30

Abstract: The present invention provides a real-time clock circuit (54), comprising: an oscillator (122); and a counter (124), coupled to an output of the oscillator (122), for generating a real-time clock value. In a first mode the oscillator (122) is configured to generate oscillations and the counter (124) is configured to increment the real-time clock value based on the oscillations. In a second mode the oscillator (122) is stopped, and the counter (124) is configured to retain the real-time clock value at a frozen value.

Abstract translation: 本发明提供了一种实时时钟电路（54），包括：振荡器（122）; 和耦合到振荡器（122）的输出的计数器（124），用于产生实时时钟值。 在第一模式中，振荡器（122）被配置为产生振荡，并且计数器（124）被配置为基于振荡来增加实时时钟值。 在第二模式中，振荡器（122）停止，并且计数器（124）被配置为将实时时钟值保持在冻结值。