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    TRANSISTOR WITH MULTI-LEVEL SELF-ALIGNED GATE AND SOURCE/DRAIN TERMINALS AND METHODS
    111.
    发明申请
    TRANSISTOR WITH MULTI-LEVEL SELF-ALIGNED GATE AND SOURCE/DRAIN TERMINALS AND METHODS 有权

    公开(公告)号：US20220223694A1

    公开(公告)日：2022-07-14

    申请号：US17146513

    申请日：2021-01-12

    Applicant: GLOBALFOUNDRIES U.S. Inc.

    Inventor： Johnatan A. Kantarovsky ,  Mark D. Levy ,  Jeonghyun Hwang ,  Siva P. Adusumilli ,  Ajay Raman

    IPC: H01L29/40 ,  H01L29/778 ,  H01L29/66 ,  H01L29/417 ,  H01L29/423 ,  H01L21/768

    Abstract: Disclosed are a transistor and a method for forming the transistor. The method includes concurrently forming gate and source/drain openings through an uppermost layer (i.e., a dielectric layer) in a stack of layers. The method can further include: depositing and patterning gate conductor material so that a first gate section is in the gate opening and a second gate section is above the gate opening and so that the source/drain openings are exposed; extending the depth of the source/drain openings; and depositing and patterning source/drain conductor material so that a first source/drain section is in each source/drain opening and a second source/drain section is above each source/drain opening. Alternatively, the method can include: forming a plug in the gate opening and sidewall spacers in the source/drain openings; extending the depth of source/drain openings; depositing and patterning the source/drain conductor material; and subsequently depositing and patterning the gate conductor material.

    SEMICONDUCTOR STRUCTURE WITH IN-DEVICE HIGH RESISTIVITY POLYCRYSTALLINE SEMICONDUCTOR ELEMENT AND METHOD
    112.
    发明申请
    SEMICONDUCTOR STRUCTURE WITH IN-DEVICE HIGH RESISTIVITY POLYCRYSTALLINE SEMICONDUCTOR ELEMENT AND METHOD 有权

    公开(公告)号：US20220181501A1

    公开(公告)日：2022-06-09

    申请号：US17114554

    申请日：2020-12-08

    Applicant: GLOBALFOUNDRIES U.S. Inc.

    Inventor： Siva P. Adusumilli ,  John J. Ellis-Monaghan ,  Steven M. Shank ,  Yves T. Ngu ,  Michael J. Zierak

    IPC: H01L29/786 ,  H01L29/04 ,  H01L21/02 ,  H01L21/8234

    Abstract: Disclosed is a structure including a semiconductor layer with a device area and, within the device area, a monocrystalline portion and polycrystalline portion(s) that extend through the monocrystalline portion. The structure includes an active device including a device component, which is in device area and which includes polycrystalline portion(s). For example, the device can be a field effect transistor (FET) (e.g., a simple FET or a multi-finger FET for a low noise amplifier or RF switch) with at least one source/drain region, which is in the device area and which includes at least one polycrystalline portion that extends through the monocrystalline portion. The embodiments can vary with regard to the type of structure (e.g., bulk or SOI), with regard to the type of device therein, and also with regard to the number, size, shape, location, orientation, etc. of the polycrystalline portion(s). Also disclosed is a method for forming the structure.

    Buried damage layers for electrical isolation
    113.
    发明授权
    Buried damage layers for electrical isolation 有权

    公开(公告)号：US11322357B2

    公开(公告)日：2022-05-03

    申请号：US16806383

    申请日：2020-03-02

    Applicant: GLOBALFOUNDRIES U.S. Inc.

    Inventor： Siva P. Adusumilli ,  Anthony K. Stamper ,  Michel J. Abou-Khalil ,  John J. Ellis-Monaghan ,  Bojidha Babu

    IPC: H01L21/265 ,  H01L21/762 ,  H01L21/324 ,  H01L29/04

    Abstract: Structures including electrical isolation and methods of forming a structure including electrical isolation. A first polycrystalline layer is located in a substrate, and a second polycrystalline layer is positioned between the first polycrystalline layer and a top surface of the substrate. The substrate includes a first portion of the single-crystal semiconductor material that is positioned between the second polycrystalline layer and the top surface of the substrate. The substrate includes a second portion of the single-crystal semiconductor material that is positioned between the first polycrystalline layer and the second polycrystalline layer. The first polycrystalline layer has a thickness. The second polycrystalline layer has a portion with a thickness that is greater than the thickness of the first polycrystalline layer.

    Epitaxial growth constrained by a template
    114.
    发明授权
    Epitaxial growth constrained by a template 有权

    公开(公告)号：US11195715B2

    公开(公告)日：2021-12-07

    申请号：US16821228

    申请日：2020-03-17

    Applicant: GLOBALFOUNDRIES U.S. Inc.

    Inventor： Siva P. Adusumilli ,  Cameron Luce ,  Ramsey Hazbun ,  Mark Levy ,  Anthony K. Stamper ,  Alvin J. Joseph

    IPC: H01L21/02 ,  H01L21/762 ,  H01L21/324

    Abstract: Methods of forming structures with electrical isolation. A dielectric layer is formed over a semiconductor substrate, openings are patterned in the dielectric layer that extend to the semiconductor substrate, and a semiconductor material is epitaxially grown from portions of the semiconductor substrate that are respectively exposed inside the openings. The semiconductor material, during growth, defines a semiconductor layer that includes first portions respectively coincident with the openings and second portions that laterally grow from the first portions to merge over a top surface of the dielectric layer. A modified layer containing a trap-rich semiconductor material is formed in the semiconductor substrate.

    SEMICONDUCTOR STRUCTURE WITH SEMICONDUCTOR-ON-INSULATOR REGION AND METHOD
    118.
    发明申请
    SEMICONDUCTOR STRUCTURE WITH SEMICONDUCTOR-ON-INSULATOR REGION AND METHOD 有权

    公开(公告)号：US20210287902A1

    公开(公告)日：2021-09-16

    申请号：US16815070

    申请日：2020-03-11

    Applicant: GLOBALFOUNDRIES U.S. Inc.

    Inventor： Ramsey Hazbun ,  Alvin J. Joseph ,  Siva P. Adusumilli ,  Cameron Luce

    IPC: H01L21/02

    Abstract: Disclosed are semiconductor structure embodiments of a semiconductor-on-insulator region on a bulk substrate. The semiconductor-on-insulator region includes an upper semiconductor layer above and physically separated from the substrate by insulator-containing cavities (e.g., by dielectric layer and/or a pocket of trapped air, of trapped gas, or under vacuum) and, optionally, by a lower semiconductor layer. Disclosed method embodiments include forming openings that extend vertically through the upper semiconductor layer, through a sacrificial semiconductor layer and, optionally, through a lower semiconductor layer to the substrate. Then, a selective isotropic etch process is performed to form cavities, which extend laterally off the sides of the openings into the sacrificial semiconductor layer. Depending upon the embodiments, different process steps are further performed to form plugs in at least the upper portions of the openings and insulators (including dielectric layers and/or a pocket of trapped air, of trapped gas or under vacuum) in the cavities.

    SILICON PHOTONIC COMPONENTS FABRICATED USING A BULK SUBSTRATE
    120.
    发明申请
    SILICON PHOTONIC COMPONENTS FABRICATED USING A BULK SUBSTRATE 有权

    公开(公告)号：US20210132461A1

    公开(公告)日：2021-05-06

    申请号：US16674711

    申请日：2019-11-05

    Applicant: GLOBALFOUNDRIES U.S. Inc.

    Inventor： Vibhor Jain ,  Siva P. Adusumilli ,  John J. Ellis-Monaghan

    IPC: G02F1/225 ,  H01L31/0232

    Abstract: Structures including a photodetector and methods of fabricating such structures. A substrate, which is composed of a semiconductor material, includes a first trench, a second trench, and a pillar of the semiconductor material that is laterally positioned between the first trench and the second trench. A first portion of a dielectric layer is located in the first trench and a second portion of the dielectric layer is located in the second trench. A waveguide core is coupled to the pillar at a top surface of the substrate.

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