公开(公告)号：US20200220017A1

公开(公告)日：2020-07-09

申请号：US16631363

申请日：2017-09-29

Applicant: INTEL CORPORATION

Inventor： Willy Rachmady ,  Matthew V. Metz ,  Gilbert Dewey ,  Nancy Zelick ,  Harold Kennel ,  Nicholas G. Minutillo ,  Cheng-Ying Huang

IPC: H01L29/78 ,  H01L21/8238 ,  H01L29/66

Abstract: A transistor includes a semiconductor fin with a subfin layer of a subfin material selected from a first group III-V compound a channel layer of a channel material directly on the subfin layer and extending upwardly therefrom, the channel material being a second group III-V compound different from the first group III-V compound. A gate structure is in direct contact with the channel layer of the semiconductor fin, where the gate structure is further in direct contact with one of (i) a top surface of the subfin layer, the top surface being exposed where the channel layer meets the subfin layer because the channel layer is narrower than the subfin layer, or (ii) a liner layer of liner material in direct contact with opposing sidewalls of the subfin layer, the liner material being distinct from the first and second group III-V compounds.

公开(公告)号：US20200098757A1

公开(公告)日：2020-03-26

申请号：US16139684

申请日：2018-09-24

Applicant: INTEL CORPORATION

Inventor： Willy Rachmady ,  Matthew Metz ,  Gilbert Dewey ,  Nicholas Minutillo ,  Cheng-Ying Huang ,  Jack Kavalieros ,  Anand Murthy ,  Tahir Ghani

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/10 ,  H01L29/423 ,  H01L29/207 ,  H01L29/08 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8238

Abstract: An integrated circuit with at least one transistor is formed using a buffer structure on the substrate. The buffer structure includes one or more layers of buffer material and comprises indium, gallium, and phosphorous. A ratio of indium to gallium in the buffer structure increases from a lower value to a higher value such that the buffer structure has small changes in lattice constant to control relaxation and defects. A source and a drain are on top of the buffer structure and a body of Group III-V semiconductor material extends between and connects the source and the drain. A gate structure wrapped around the body, the gate structure including a gate electrode and a gate dielectric, wherein the gate dielectric is between the body and the gate electrode.

公开(公告)号：US20200098756A1

公开(公告)日：2020-03-26

申请号：US16138356

申请日：2018-09-21

Applicant: INTEL CORPORATION

Inventor： Aaron Lilak ,  Stephen Cea ,  Gilbert Dewey ,  Willy Rachmady ,  Roza Kotlyar ,  Rishabh Mehandru ,  Sean Ma ,  Ehren Mannebach ,  Anh Phan ,  Cheng-Ying Huang

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L29/16 ,  H01L29/423 ,  H01L29/10 ,  H01L29/08 ,  H01L21/8238

Abstract: A nanowire transistor structure has a first device region with a first body of semiconductor material having a first cross-sectional shape. A second device region has a second body with a second cross-sectional shape different from the first cross-sectional shape. The first device section is vertically above or below the second device section with the bodies extending horizontally between a source and drain. A first gate structure is wrapped around the first body and a second gate structure is wrapped around the second body. Differences in the geometries of the nanowires can be used to optimize performance in the first device section independently of the second device section.

公开(公告)号：US10559683B2

公开(公告)日：2020-02-11

申请号：US15504171

申请日：2014-09-19

Applicant: Intel Corporation

Inventor： Chandra S. Mohapatra ,  Anand S. Murthy ,  Glenn A. Glass ,  Tahir Ghani ,  Willy Rachmady ,  Gilbert Dewey ,  Matthew V. Metz ,  Jack T. Kavalieros

IPC: H01L29/78 ,  H01L29/786 ,  H01L29/10 ,  H01L21/762 ,  H01L29/06 ,  H01L29/66 ,  H01L29/201 ,  H01L29/423

Abstract: Transistor devices having a buffer between an active channel and a substrate, which may include the active channel comprising a low band-gap material on a sub-structure, e.g. a buffer, between the active channel and the substrate. The sub-structure may comprise a high band-gap material having a desired conduction band offset, such that leakage may be arrested without significant impact on electronic mobility within the active channel. In an embodiment, the active channel and the sub-structure may be formed in a narrow trench, such that defects due to lattice mismatch between the active channel and the sub-structure are terminated in the sub-structure. In a further embodiment, the sub-structure may be removed to form either a void between the active channel and the substrate, or an insulative material may be disposed between the active channel and the substrate, such that the void or the insulative material form an insulative buffer.

公开(公告)号：US20200006510A1

公开(公告)日：2020-01-02

申请号：US16490866

申请日：2017-03-31

Applicant: Intel Corporation

Inventor： Cheng-Ying Huang ,  Sean T. Ma ,  Willy Rachmady ,  Gilbert Dewey ,  Matthew V. Metz ,  Harold W. Kennel ,  Jack T. Kavalieros ,  Anand S. Murthy ,  Tahir Ghani

IPC: H01L29/423 ,  H01L29/786 ,  H01L29/04 ,  H01L29/66

Abstract: In various embodiments, the disclosure describes transistors having non-vertical gates. In one embodiment, the non-vertical gates can have a curved or wide angle gate in order to reduce the electric field crowing on the drain side of the gate edge and/or portions having corners and thereby reduce leakage current in the transistor. In one embodiment, the non-vertical gate can be generated by one or more etching steps (for example, isotropic etching steps) of an underlying channel during the fabrication of a transistor having the non-vertical gate. In one embodiment, the non-vertical gate can be generated by one or more directional etching steps that may expose various facets having predetermined orientations of a source and/or drain associated with the transistor.

公开(公告)号：US10461193B2

公开(公告)日：2019-10-29

申请号：US15575322

申请日：2015-05-27

Applicant: Intel Corporation

Inventor： Chandra S. Mohapatra ,  Gilbert Dewey ,  Anand S. Murthy ,  Glenn A. Glass ,  Willy Rachmady ,  Jack T. Kavalieros ,  Tahir Ghani ,  Matthew V. Metz

IPC: H01L29/00 ,  H01L29/786 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/10

Abstract: Transistor devices may be formed having a buffer between an active channel and a substrate, wherein the active channel and a portion of the buffer form a gated region. The active channel may comprise a low band-gap material on a sub-structure, e.g. the buffer, between the active channel and the substrate. The sub-structure may comprise a high band-gap material having a desired conduction band offset, such that leakage may be arrested without significant impact on electron mobility within the active channel. In an embodiment, the active channel and the sub-structure may be formed in a narrow trench, such that defects due to lattice mismatch between the active channel and the sub-structure are terminated in the sub-structure.

公开(公告)号：US20190305138A1

公开(公告)日：2019-10-03

申请号：US15942169

申请日：2018-03-30

Applicant: Intel Corporation

Inventor： Abhishek A. Sharma ,  Sean T. Ma ,  Van H. Le ,  Jack T. Kavalieros ,  Gilbert Dewey

IPC: H01L29/786 ,  H01L29/66 ,  H01L29/06 ,  H01L29/423

Abstract: Described is a thin film transistor which comprises: a dielectric comprising a dielectric material; a first structure adjacent to the dielectric, the first structure comprising a first material; a second structure adjacent to the first structure, the second structure comprising a second material wherein the second material is doped; a second dielectric adjacent to the second structure; a gate comprising a metal adjacent to the second dielectric; a spacer partially adjacent to the gate and the second dielectric; and a contact adjacent to the spacer.

公开(公告)号：US10411122B2

公开(公告)日：2019-09-10

申请号：US16110458

申请日：2018-08-23

Applicant: Intel Corporation

Inventor： Gilbert Dewey ,  Marko Radosavljevic ,  Ravi Pillarisetty ,  Matthew V. Metz

IPC: H01L29/775 ,  B82Y10/00 ,  B82Y40/00 ,  H01L29/423 ,  H01L29/51 ,  H01L29/66 ,  H01L29/06 ,  H01L29/15 ,  H01L29/205 ,  H01L29/49 ,  H01L29/786

Abstract: Semiconductor devices having group III-V material active regions and graded gate dielectrics and methods of fabricating such devices are described. In an example, a semiconductor device includes a group III-V material channel region disposed above a substrate. A gate stack is disposed on the group III-V material channel region. The gate stack includes a graded high-k gate dielectric layer disposed directly between the III-V material channel region and a gate electrode. The graded high-k gate dielectric layer has a lower dielectric constant proximate the III-V material channel region and has a higher dielectric constant proximate the gate electrode. Source/drain regions are disposed on either side of the gate stack.

公开(公告)号：US10347767B2

公开(公告)日：2019-07-09

申请号：US15570742

申请日：2015-06-16

Applicant: Intel Corporation

Inventor： Willy Rachmady ,  Matthew V. Metz ,  Van H. Le ,  Ravi Pillarisetty ,  Gilbert Dewey ,  Jack T. Kavalieros ,  Ashish Agrawal

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/10 ,  H01L21/02 ,  H01L21/762 ,  H01L29/06

Abstract: A subfin layer is deposited in a trench in an insulating layer on the substrate. A fin is deposited on the subfin layer. The fin has a top portion and opposing sidewalls. The fin comprises a first semiconductor material. The subfin layer comprises a III-V semiconductor material.

公开(公告)号：US10340374B2

公开(公告)日：2019-07-02

申请号：US15755450

申请日：2015-09-25

Applicant: Intel Corporation

Inventor： Gilbert Dewey ,  Willy Rachmady ,  Matthew V. Metz ,  Chandra S. Mohapatra ,  Sean T. Ma ,  Jack T. Kavalieros ,  Anand S. Murthy ,  Tahir Ghani

IPC: H01L29/66 ,  H01L29/778 ,  H01L29/775 ,  H01L29/201 ,  H01L21/8238 ,  H01L21/8258 ,  H01L27/092 ,  H01L29/10 ,  H01L29/205 ,  H01L29/423 ,  H01L29/78 ,  B82Y10/00 ,  H01L29/06

Abstract: Monolithic FETs including a channel region of a first semiconductor material disposed over a substrate. While a mask, such as a gate stack or sacrificial gate stack, is covering the channel region, an impurity-doped compositionally graded semiconductor is grown, for example on at least a drain end of the channel region to introduce a carrier-blocking conduction band offset and/or a wider band gap within the drain region of the transistor. In some embodiments, the compositional grade induces a carrier-blocking band offset of at least 0.25 eV. The wider band gap and/or band offset contributes to a reduced gate induced drain leakage (GIDL). The impurity-doped semiconductor may be compositionally graded back down from the retrograded composition to a suitably narrow band gap material providing good ohmic contact. In some embodiments, the impurity-doped compositionally graded semiconductor growth is integrated into a gate-last, source/drain regrowth finFET fabrication process.