公开(公告)号：US09263540B1

公开(公告)日：2016-02-16

申请号：US14852624

申请日：2015-09-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Ling Lin ,  Chih-Sen Huang ,  Shih-Fang Tzou ,  Chien-Ting Lin ,  Yi-Wei Chen ,  Shi-Xiong Lin ,  Chun-Lung Chen ,  Kun-Yuan Liao ,  Feng-Yi Chang ,  Hsiao-Pang Chou ,  Chia-Lin Lu

IPC: H01L27/088 ,  H01L29/49 ,  H01L29/423

CPC classification number: H01L29/4966 ,  H01L21/28088 ,  H01L21/823456 ,  H01L21/82385 ,  H01L27/088 ,  H01L29/4232 ,  H01L29/517 ,  H01L29/66545

Abstract: The metal gate structure includes at least a substrate, a dielectric layer, first and second trenches, first metal layer and second metal layers, and two cap layers. In particular, the dielectric layer is disposed on the substrate, and the first and second trenches are disposed in the dielectric layer. The width of the first trench is less than the width of the second trench. The first and second metal layers are respectively disposed in the first trench and the second trench, and the height of the first metal layer is less than or equal to the height of the second metal layer. The cap layers are respectively disposed in a top surface of the first metal layer and a top surface of the second metal layer.

Abstract translation: 金属栅极结构至少包括衬底，电介质层，第一和第二沟槽，第一金属层和第二金属层以及两个盖层。 特别地，介电层设置在基板上，并且第一和第二沟槽设置在电介质层中。 第一沟槽的宽度小于第二沟槽的宽度。 第一和第二金属层分别设置在第一沟槽和第二沟槽中，第一金属层的高度小于或等于第二金属层的高度。 盖层分别设置在第一金属层的顶表面和第二金属层的顶表面中。

公开(公告)号：US09263392B1

公开(公告)日：2016-02-16

申请号：US14529129

申请日：2014-10-30

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Ling Lin ,  Chih-Sen Huang ,  Ching-Wen Hung ,  Jia-Rong Wu ,  Tsung-Hung Chang ,  Yi-Hui Lee ,  Yi-Wei Chen

IPC: H01L21/336 ,  H01L23/535 ,  H01L29/78 ,  H01L21/8234 ,  H01L21/768 ,  H01L21/02 ,  H01L21/311

CPC classification number: H01L21/31144 ,  H01L21/0217 ,  H01L21/7682 ,  H01L21/76834 ,  H01L21/76897 ,  H01L21/823475 ,  H01L23/485 ,  H01L29/41791 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/785 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a metal gate thereon and an interlayer dielectric (ILD) layer around the metal gate; removing part of the metal gate to form a recess; and depositing a mask layer in the recess and on the ILD layer while forming a void in the recess.

Abstract translation: 公开了半导体器件的制造方法。 该方法包括以下步骤：提供其上具有金属栅极的基板和围绕金属栅极的层间电介质（ILD）层; 去除所述金属浇口的一部分以形成凹部; 以及在所述凹部中和所述ILD层上沉积掩模层，同时在所述凹部中形成空隙。

公开(公告)号：US09190291B2

公开(公告)日：2015-11-17

申请号：US13934236

申请日：2013-07-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Jui Liang ,  Po-Chao Tsao ,  Jun-Jie Wang ,  Chih-Sen Huang

IPC: H01L21/311

CPC classification number: H01L21/31144 ,  H01L21/3086 ,  H01L29/66795

Abstract: A fin-shaped structure forming process includes the following step. A first mandrel and a second mandrel are formed on a substrate. A first spacer material is formed to entirely cover the first mandrel, the second mandrel and the substrate. The exposed first spacer material is etched to form a first spacer on the substrate beside the first mandrel. A second spacer material is formed to entirely cover the first mandrel, the second mandrel and the substrate. The second spacer material and the first spacer material are etched to form a second spacer on the substrate beside the second mandrel and a third spacer including the first spacer on the substrate beside the first mandrel. The layout of the second spacer and the third spacer is transferred to the substrate, so a second fin-shaped structure and a first fin-shaped structure having different widths are formed respectively.

Abstract translation: 鳍状结构形成工序包括以下工序。 第一心轴和第二心轴形成在基底上。 形成第一间隔材料以完全覆盖第一心轴，第二心轴和基底。 蚀刻暴露的第一间隔物材料以在第一心轴旁边的基底上形成第一间隔物。 形成第二间隔材料以完全覆盖第一心轴，第二心轴和基底。 蚀刻第二间隔物材料和第一间隔物材料以在第二心轴旁边的基底上形成第二间隔物，以及在第一心轴旁边的包括在基底上的第一间隔物的第三间隔物。 第二间隔物和第三间隔物的布局被转移到基底，因此分别形成具有不同宽度的第二鳍状结构和第一鳍状结构。

公开(公告)号：US20150179457A1

公开(公告)日：2015-06-25

申请号：US14639134

申请日：2015-03-05

Applicant: United Microelectronics Corp.

Inventor： Ching-Wen Hung ,  Chih-Sen Huang ,  Po-Chao Tsao ,  Shih-Fang Tzou

IPC: H01L21/28 ,  H01L21/3205 ,  H01L21/311 ,  H01L29/66

CPC classification number: H01L21/28079 ,  H01L21/28008 ,  H01L21/28088 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/32053 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76897 ,  H01L23/485 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for fabricating a semiconductor device includes the following steps. First, a first interlayer dielectric is formed on a substrate. Then, a gate electrode is formed on the substrate so that the periphery of the gate electrode is surrounded by the first interlayer dielectric. Afterwards, a patterned mask layer is formed on the gate electrode, and a bottom surface of the patterned mask layer is level with a top surface of the first interlayer dielectric. A spacer is then formed on each sidewall of the gate electrode. Subsequently, a second interlayer dielectric is formed to cover a top surface and each side surface of the patterned mask layer. Finally, a self-aligned contact structure is formed in the first interlayer dielectric and the second interlayer dielectric.

Abstract translation: 一种制造半导体器件的方法包括以下步骤。 首先，在基板上形成第一层间电介质。 然后，在基板上形成栅电极，使得栅电极的周围被第一层间电介质包围。 之后，在栅电极上形成图案化掩模层，并且图案化掩模层的底表面与第一层间电介质的顶表面平齐。 然后在栅电极的每个侧壁上形成间隔物。 随后，形成第二层间电介质以覆盖图案化掩模层的顶表面和每个侧表面。 最后，在第一层间电介质和第二层间电介质中形成自对准接触结构。

公开(公告)号：US20150118836A1

公开(公告)日：2015-04-30

申请号：US14064722

申请日：2013-10-28

Applicant: United Microelectronics Corp.

Inventor： Ching-Ling Lin ,  Chih-Sen Huang ,  Jia-Rong Wu ,  Ching-Wen Hung ,  Po-Chao Tsao

IPC: H01L29/66 ,  H01L21/768

CPC classification number: H01L29/66545 ,  H01L21/28247 ,  H01L21/76834 ,  H01L21/76897 ,  H01L29/41791 ,  H01L29/66628 ,  H01L29/66795 ,  H01L29/7848

Abstract: A method of fabricating a semiconductor device is disclosed. Provided is a substrate having a dummy gate formed thereon, a spacer on a sidewall of the dummy gate and a first dielectric layer surrounding the spacer. The dummy gate is removed to form a gate trench. A gate dielectric layer and at least one work function layer is formed in the gate trench. The work function layer and the gate dielectric layer are pulled down, and a portion of the spacer is laterally removed at the same time to widen a top portion of the gate trench. A low-resistivity metal layer is formed in a bottom portion of the gate trench. A hard mask layer is formed in the widened top portion of the gate trench.

Abstract translation: 公开了制造半导体器件的方法。 提供了一种其上形成有虚拟栅极的基板，在虚拟栅极的侧壁上的间隔物和围绕间隔物的第一介电层。 去除伪栅极以形成栅极沟槽。 栅极介电层和至少一个功函数层形成在栅极沟槽中。 功函数层和栅介质层被下拉，并且间隔件的一部分同时被横向去除，以加宽栅沟槽的顶部。 在栅极沟槽的底部形成低电阻率金属层。 在栅沟槽的加宽的顶部形成有硬掩模层。

公开(公告)号：US20150118835A1

公开(公告)日：2015-04-30

申请号：US14062909

申请日：2013-10-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Ling Lin ,  Chih-Sen Huang ,  Po-Chao Tsao ,  Ching-Wen Hung ,  Jia-Rong Wu ,  Chien-Ting Lin

IPC: H01L21/768 ,  H01L29/66

CPC classification number: H01L29/66477 ,  H01L21/28247 ,  H01L21/76834 ,  H01L21/76897 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/7848

Abstract: A method for manufacturing a semiconductor device includes following steps. A substrate having at least a transistor embedded in an insulating material formed thereon is provided. The transistor includes a metal gate. Next, an etching process is performed to remove a portion of the metal gate to form a recess and to remove a portion of the insulating material to form a tapered part. After forming the recess and the tapered part of the insulating material, a hard mask layer is formed on the substrate to fill up the recess. Subsequently, the hard mask layer is planarized.

Abstract translation: 一种制造半导体器件的方法包括以下步骤。 提供了至少具有嵌入在其上形成绝缘材料的晶体管的衬底。 晶体管包括金属栅极。 接下来，进行蚀刻处理以去除金属栅极的一部分以形成凹部并且去除绝缘材料的一部分以形成锥形部分。 在形成凹部和绝缘材料的锥形部分之后，在基板上形成硬掩模层以填充凹部。 随后，硬掩模层被平坦化。

公开(公告)号：US20150008524A1

公开(公告)日：2015-01-08

申请号：US13933141

申请日：2013-07-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Wen Hung ,  Chih-Sen Huang

IPC: H01L27/088 ,  H01L29/66

CPC classification number: H01L27/088 ,  H01L27/0207 ,  H01L27/0886 ,  H01L27/11807

Abstract: An integrated circuit device structure, in which, a diffusion region is formed in a substrate, an extension conductor structure is contacted with the diffusion region and extended externally to a position along a surface of the substrate, the position is outside the diffusion region, another extension conductor structure is contacted with the diffusion region, a jumper conductor structure is disposed over the substrate and on these two extension conductor structures for electrically connecting these two extension conductor structures, the jumper conductor structure may be over one or more gate structures, a contact structure penetrates through a dielectric layer to be contacted with the jumper conductor structure, and a metal conductor line is contacted with the contact structure.

Abstract translation: 一种集成电路器件结构，其中在衬底中形成扩散区域，延伸导体结构与扩散区域接触并且在外部延伸到沿着衬底表面的位置，该位置在扩散区域外部，另一个 延伸导体结构与扩散区域接触，跳线导体结构设置在基板上方，并且在这两个延伸导体结构上用于电连接这两个延伸导体结构，跳线导体结构可以在一个或多个栅结构上，触点 结构穿透介电层以与跳线导体结构接触，并且金属导体线与接触结构接触。

公开(公告)号：US08921947B1

公开(公告)日：2014-12-30

申请号：US13913617

申请日：2013-06-10

Applicant: United Microelectronics Corp.

Inventor： Ching-Wen Hung ,  Chih-Sen Huang ,  Yi-Ching Wu

IPC: H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119 ,  H01L29/792 ,  H01L27/10 ,  H01L29/739 ,  H01L21/768 ,  H01L29/45

CPC classification number: H01L29/458 ,  H01L21/28518 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76895 ,  H01L21/76897 ,  H01L23/485 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for manufacturing a semiconductor device and a device manufactured using the same are provided. A substrate with plural metal gates formed thereon is provided, wherein the adjacent metal gates are separated by insulation. A sacrificial layer is formed for capping the metal gates and the insulation, and the sacrificial layer and the insulation are patterned to form at least an opening for exposing the substrate. A silicide is formed corresponding to the opening at the substrate, and a conductive contact is formed in the opening. The conductive contact has a top area with a second diameter CD2 for opening the insulation. A patterned dielectric layer, further formed on the metal gates, the insulation and the conductive contact, at least has a first M0 opening with a third diameter CD3 for exposing the conductive contact, wherein CD2>CD3.

Abstract translation: 提供一种制造半导体器件的方法和使用其制造的器件。 提供了形成有多个金属栅的衬底，其中相邻的金属栅极被隔离隔开。 形成用于对金属栅极和绝缘体进行封盖的牺牲层，并且牺牲层和绝缘体被图案化以形成用于暴露衬底的至少一个开口。 对应于基板上的开口形成硅化物，并且在开口中形成导电接触。 导电触点具有顶部区域，具有用于打开绝缘体的第二直径CD2。 进一步形成在金属栅极上的绝缘层和导电接触件的图案化电介质层至少具有第三直径CD3的第一M0开口，用于暴露导电接触，其中CD2> CD3。

公开(公告)号：US08921226B2

公开(公告)日：2014-12-30

申请号：US13740289

申请日：2013-01-14

Applicant: United Microelectronics Corp.

Inventor： Ching-Wen Hung ,  En-Chiuan Liou ,  Chih-Sen Huang ,  Po-Chao Tsao

IPC: H01L21/768

CPC classification number: H01L21/76816 ,  H01L21/28518 ,  H01L21/31144 ,  H01L21/76814 ,  H01L21/76855 ,  H01L23/485 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming a semiconductor structure having at least a contact plug includes the following steps. At first, at least a transistor and an inter-layer dielectric (ILD) layer are formed on a substrate, and the transistor includes a gate structure and two source/drain regions. Subsequently, a cap layer is formed on the ILD layer and on the transistor, and a plurality of openings that penetrate through the cap layer and the ILD layer until reaching the source/drain regions are formed. Afterward, a conductive layer is formed to cover the cap layer and fill the openings, and a part of the conductive layer is further removed for forming a plurality of first contact plugs, wherein a top surface of a remaining conductive layer and a top surface of a remaining cap layer are coplanar, and the remaining cap layer totally covers a top surface of the gate structure.

Abstract translation: 形成至少具有接触插塞的半导体结构的方法包括以下步骤。 首先，在衬底上形成至少一个晶体管和层间电介质（ILD）层，并且晶体管包括栅极结构和两个源极/漏极区域。 随后，在ILD层和晶体管上形成覆盖层，并且形成穿过覆盖层和ILD层的多个开口直到到达源/漏区。 之后，形成导电层以覆盖盖层并填充开口，并且进一步去除导电层的一部分以形成多个第一接触塞，其中剩余导电层的顶表面和顶表面 剩余的盖层是共面的，剩余的盖层完全覆盖栅极结构的顶表面。

公开(公告)号：US20140361381A1

公开(公告)日：2014-12-11

申请号：US13913617

申请日：2013-06-10

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Wen Hung ,  Chih-Sen Huang ,  Yi-Ching Wu

IPC: H01L21/768 ,  H01L29/45

CPC classification number: H01L29/458 ,  H01L21/28518 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76895 ,  H01L21/76897 ,  H01L23/485 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for manufacturing a semiconductor device and a device manufactured using the same are provided. A substrate with plural metal gates formed thereon is provided, wherein the adjacent metal gates are separated by insulation. A sacrificial layer is formed for capping the metal gates and the insulation, and the sacrificial layer and the insulation are patterned to form at least an opening for exposing the substrate. A silicide is formed corresponding to the opening at the substrate, and a conductive contact is formed in the opening. The conductive contact has a top area with a second diameter CD2 for opening the insulation. A patterned dielectric layer, further formed on the metal gates, the insulation and the conductive contact, at least has a first M0 opening with a third diameter CD3 for exposing the conductive contact, wherein CD2>CD3.

Abstract translation: 提供一种制造半导体器件的方法和使用其制造的器件。 提供了形成有多个金属栅的衬底，其中相邻的金属栅极被隔离隔开。 形成用于对金属栅极和绝缘体进行封盖的牺牲层，并且牺牲层和绝缘体被图案化以形成用于暴露衬底的至少一个开口。 对应于基板上的开口形成硅化物，并且在开口中形成导电接触。 导电触点具有顶部区域，具有用于打开绝缘体的第二直径CD2。 进一步形成在金属栅极上的绝缘层和导电接触件的图案化电介质层至少具有第三直径CD3的第一M0开口，用于暴露导电接触，其中CD2> CD3。