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    Memory devices with selectable access type and systems and methods using the same
    112.
    发明公开
    Memory devices with selectable access type and systems and methods using the same 失效
    具有选择性接入方式和系统及其方法的存储器设备

    公开(公告)号：EP0771007A3

    公开(公告)日：1997-11-26

    申请号：EP96307293.9

    申请日：1996-10-04

    Applicant: CIRRUS LOGIC, INC.

    Inventor： Rao, G.R. Mohan

    IPC: G11C7/00

    CPC classification number: G11C7/1036 ,  G11C7/1045

    Abstract: A memory 200 including an array 201 of rows and columns of memory cells. Row decoder circuitry 211 is provided for selecting in response to a row address a row in array 201 for access. Column decoder circuitry 205 is provided for selecting at least one location within a first group of columns along the selected row in array 201 in response to a column address. At least one shift register 207 is provided for allowing serial access to one of the cells within a second group of columns along the selected row.

    AN IMPROVED MEMORY ARCHITECTURE AND DEVICES, SYSTEMS AND METHODS UTILIZING THE SAME
    113.
    发明公开
    AN IMPROVED MEMORY ARCHITECTURE AND DEVICES, SYSTEMS AND METHODS UTILIZING THE SAME 失效
    改进SPEICHERARCHTITEKTUR和设备，系统和方法这个架构使用

    公开(公告)号：EP0781443A1

    公开(公告)日：1997-07-02

    申请号：EP95935051.0

    申请日：1995-09-11

    Applicant: CIRRUS LOGIC, INC.

    Inventor： RAO, G., R., Mohan

    IPC: G11C11 ,  G06F3 ,  G09G5 ,  G11C7

    CPC classification number: G11C7/1036

    Abstract: A memory (200) is provided which includes a plurality of self-contained memory units (201) for storing data. A plurality of shift registers (211) are provided, each including a first parallel port coupled to a data port of a corresponding one of the self-contained memory units (201). Interconnection circuitry (212) is coupled to a parallel data port of each of the shift registers. Control circuitry (208, 213) is provided which is operable to control the exchange of data between a selected one of the memory units and the interconnection circuitry (212) via the shift register (211) coupled to the selected memory unit (201).

    Semiconductor memory device
    114.
    发明公开
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：EP0590953A3

    公开(公告)日：1994-08-03

    申请号：EP93307716.6

    申请日：1993-09-29

    Applicant: NEC CORPORATION

    Inventor： Okimura, Yasunori, c/o NEC IC Microcomp. Syst. Ltd

    IPC: G11C7/00

    CPC classification number: G11C7/1036

    Abstract: A semiconductor memory circuit includes a memory cell array for storing data, and a bit structure selection circuit for performing a data transfer between the memory cell array and an external device by constructing the data in units of one bit or in units of two bits. The bit structure selection circuit includes a selector for selectively modifying a phase of a first clock signal and a second clock signal in response to a mode signal, and shift register for modifying a shift width of a memory selection signal in response to the first clock signal and the second clock signal supplied through the selector.

    Abstract translation: 半导体存储器电路包括用于存储数据的存储器单元阵列以及用于通过以1位为单位或以2位为单位构造数据来执行存储器单元阵列与外部设备之间的数据传输的位结构选择电路。 位结构选择电路包括响应于模式信号选择性地修改第一时钟信号和第二时钟信号的相位的选择器，以及响应于第一时钟信号修改存储器选择信号的移位宽度的移位寄存器 和通过选择器提供的第二时钟信号。

    SHIFT REGISTER UNIT, GATE LINE DRIVING APPARATUS AND DRIVING METHOD
    116.
    发明公开
    SHIFT REGISTER UNIT, GATE LINE DRIVING APPARATUS AND DRIVING METHOD 审中-公开

    公开(公告)号：EP3361472A1

    公开(公告)日：2018-08-15

    申请号：EP16852863.6

    申请日：2016-09-30

    Applicant: BOE Technology Group Co., Ltd. ,  Beijing BOE Display Technology Co., Ltd.

    Inventor： WANG, Zheng

    IPC: G09G3/36

    CPC classification number: G09G3/3685 ,  G09G3/3677 ,  G09G2310/0283 ,  G09G2310/0286 ,  G11C7/1036 ,  G11C7/20 ,  G11C19/28 ,  G11C19/30 ,  G11C29/022 ,  G11C29/86

    Abstract: A shift register unit, a gate line driving device includes multiple stages of the shift register units, and a driving method for being applied to the shift register unit; the shift register unit includes: an input module (200) connected between an input terminal (INPUT) and a pull-up node (PU), and configured to charge the pull-up node (PU); an output module (205) connected between the pull-up node (PU), a first clock signal terminal (CK) and an output terminal (OUTPUT), and configured to output to the output terminal (OUTPUT) a first clock signal received at the first clock signal terminal (CK); a pull-up node reset module (215) connected between a reset terminal (RESET-IN), a pull-down node (PD) and the pull-up node (PU), and configured to reset the pull-up node (PU); and an output reset module (220) connected between a second clock signal terminal (CKB), the pull-down node (PD) and the output terminal (OUTPUT), and configured to reset the output terminal (OUTPUT). The shift register unit, a gate line driving device and a driving method can downsize an overall structure of the GOA, reduce power consumption, decrease signal delay, improve signal waveform, and also enhance reliability of the GOA circuit in entirety.

    TIME-CONSTRAINED DATA COPYING BETWEEN STORAGE MEDIA
    117.
    发明公开
    TIME-CONSTRAINED DATA COPYING BETWEEN STORAGE MEDIA 审中-公开
    存储介质之间的时间约束数据复制

    公开(公告)号：EP3158458A1

    公开(公告)日：2017-04-26

    申请号：EP15732084.7

    申请日：2015-05-28

    Applicant: Qualcomm Incorporated

    Inventor： AMARILIO, Lior ,  KHAZIN, Alexander

    IPC: G06F13/38 ,  G06F13/42

    CPC classification number: G11C7/1075 ,  G06F13/287 ,  G06F13/364 ,  G06F13/385 ,  G06F13/4022 ,  G06F13/4282 ,  G06F13/4295 ,  G11C7/1036

    Abstract: Time-constrained data copying between storage media is disclosed. When an electronic device is engaged in real-time operations, multiple data blocks may need to be copied from one storage medium to another storage medium within certain time constraints. In this regard, a data port is operatively controlled by a plurality of registers of a first register bank. The plurality of registers is copied from the first register bank to a second register bank within a temporal limit and while the data port remains under control of the plurality of registers being copied. By copying the plurality of registers within the temporal limit, it is possible to prevent operational interruption in the data port and reduce bandwidth overhead associated with the register copying operation.

    Abstract translation: 公开了存储介质之间时间受限的数据复制。 当电子设备进行实时操作时，可能需要在一定的时间限制内将多个数据块从一个存储介质复制到另一个存储介质。 就这一点而言，数据端口由第一寄存器组的多个寄存器可操作地控制。 多个寄存器在时间限制内从第一寄存器组复制到第二寄存器组，并且数据端口保持在被复制的多个寄存器的控制下。 通过在时间限制内复制多个寄存器，可以防止数据端口中的操作中断并减少与寄存器复制操作相关的带宽开销。

    MULTIPLE REGISTER MEMORY ACCESS INSTRUCTIONS, PROCESSORS, METHODS, AND SYSTEMS
    118.
    发明公开
    MULTIPLE REGISTER MEMORY ACCESS INSTRUCTIONS, PROCESSORS, METHODS, AND SYSTEMS 审中-公开
    存储器访问命令，处理器，方法，并与多种寄存器的系统

    公开(公告)号：EP3014416A4

    公开(公告)日：2017-02-22

    申请号：EP14817022

    申请日：2014-06-26

    Applicant: INTEL CORP

    Inventor： HINTON GLENN ,  TOLL BRET ,  SINGHAL RONAK

    IPC: G06F9/06 ,  G06F9/30 ,  G06F12/08

    CPC classification number: G11C7/1036 ,  G06F9/30043 ,  G06F9/30109 ,  G06F9/30163

    Abstract: A processor includes N-bit registers and a decode unit to receive a multiple register memory access instruction. The multiple register memory access instruction is to indicate a memory location and a register. The processor includes a memory access unit coupled with the decode unit and with the N-bit registers. The memory access unit is to perform a multiple register memory access operation in response to the multiple register memory access instruction. The operation is to involve N-bit data, in each of the N-bit registers comprising the indicated register. The operation is also to involve different corresponding N-bit portions of an M×N-bit line of memory corresponding to the indicated memory location. A total number of bits of the N-bit data in the N-bit registers to be involved in the multiple register memory access operation is to amount to at least half of the M×N-bits of the line of memory.

    METHODS AND APPARATUS FOR IMPROVED MEMORY ACCESS
    120.
    发明公开
    METHODS AND APPARATUS FOR IMPROVED MEMORY ACCESS 有权
    方法和提高内存器件

    公开(公告)号：EP1576445A4

    公开(公告)日：2006-08-16

    申请号：EP03810796

    申请日：2003-10-23

    Applicant: RING TECHNOLOGY ENTPR S LLC

    Inventor： LYNCH WILLIAM T ,  HERBISON DAVID J

    IPC: G11C7/10 ,  G06F13/16 ,  G11C5/00 ,  G11C29/12

    CPC classification number: G11C29/32 ,  G06F13/1673 ,  G11C7/1036 ,  G11C29/12 ,  G11C29/1201 ,  G11C2029/3202

    Abstract: A memory access scheme employing one or more sets of shift registers interconnected in series to which data may be loaded from or written into one or more memory devices. That is, data from the memory devices may be parallel loaded into the sets of shift registers and then serially shifted through the shift registers until it is output from the sets of shift registers and transferred to its destination. Additionally, the data may be read from and loaded into the memory devices to/from the sets of shift registers such that the shifting of the shift registers is uninterrupted during the reading and/or loading of data. Additionally, data from the memory devices may be loaded into two or more parallel chains of shift registers and then serially shifted through the shift register chains.

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