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    Synchronization of recency information in inclusive cache hierarchy
    1.
    发明专利
    Synchronization of recency information in inclusive cache hierarchy 有权
    包含高速缓存中的记录信息同步

    公开(公告)号：JP2007249971A

    公开(公告)日：2007-09-27

    申请号：JP2007063584

    申请日：2007-03-13

    Applicant: Intel Corp ,  インテル コーポレイション

    Inventor： SHANNON CHRISTOPHER ,  SINGHAL RONAK ,  HAMMARLUND PER ,  GARTLER HERMANN ,  HINTON GLENN

    IPC: G06F12/08 ,  G06F12/12

    CPC classification number: G06F12/123

    Abstract: PROBLEM TO BE SOLVED: To provide a method, a device, an object and a system for improving performance by reducing the possibility of eliminating a cache line of a lower-level cache frequently accessed by a processor from a higher-level cache.
    SOLUTION: The method includes the steps for: receiving a cache access request for data present in a lower-level cache line of the lower-level cache; and sending recency information regarding the lower-level cache line to a higher-level cache integrated in the lower-level cache.
    COPYRIGHT: (C)2007,JPO&INPIT

    Abstract translation: 解决的问题：提供一种方法，设备，对象和系统，用于通过降低从高级缓存中消除由处理器频繁访问的低级缓存的高速缓存线的可能性来提高性能 。 解决方案：该方法包括以下步骤：接收对存在于下级高速缓存的下级高速缓存行中的数据的高速缓存访​​问请求; 以及将关于下级高速缓存线的新近度信息发送到集成在下级高速缓存中的高级缓存。 版权所有（C）2007，JPO＆INPIT

    METHOD AND APPARATUS FOR PARTITIONING A RESOURCE BETWEEN MULTIPLE THREADS WITHIN A MULTI-THREADED PROCESSOR
    4.
    发明申请
    METHOD AND APPARATUS FOR PARTITIONING A RESOURCE BETWEEN MULTIPLE THREADS WITHIN A MULTI-THREADED PROCESSOR 审中-公开
    用于在多线程处理器中分配多个线程之间的资源的方法和装置

    公开(公告)号：WO0177820A2

    公开(公告)日：2001-10-18

    申请号：PCT/US0101577

    申请日：2001-01-16

    Applicant: INTEL CORP ,  LEE CHAN W ,  HINTON GLENN ,  KRICK ROBERT

    Inventor： LEE CHAN W ,  HINTON GLENN ,  KRICK ROBERT

    IPC: G06F9/318 ,  G06F9/38 ,  G06F9/50 ,  G06F12/12 ,  G06F9/46

    CPC classification number: G06F9/50 ,  G06F9/3017 ,  G06F9/3802 ,  G06F9/3808 ,  G06F9/382 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3851 ,  G06F9/3855 ,  G06F12/0842 ,  G06F12/121

    Abstract: A method of partitioning a memory resource, associated with a multi-threaded processor, includes defining the memory resource to include first and second portions that are dedicated to the first and second threads respectively. A third portion of the memory resource is then designated as being shared between the first and second threads. Upon receipt of an information item, (e.g., a microinstruction associated with the first thread and to be stored in the memory resource), a history of Least Recently Used (LRU) portions is examined to identify a location in either the first or the third portion, but not the second portion, as being a least recently used portion. The second portion is excluded from this examination on account of being dedicated to the second thread.

    Abstract translation: 分配与多线程处理器相关联的存储器资源的方法包括定义存储器资源以分别包括专用于第一和第二线程的第一和第二部分。 然后，内存资源的第三部分被指定为在第一和第二线程之间共享。 在接收到信息项目（例如，与第一线程相关并且要存储在存储器资源中的微指令）时，检查最近最少使用（LRU）部分的历史以识别第一或第三 部分，而不是第二部分，作为最近最少使用的部分。 第二部分由于专用于第二线程而被排除在本次考试之外。

    MULTIPLE REGISTER MEMORY ACCESS INSTRUCTIONS, PROCESSORS, METHODS, AND SYSTEMS
    5.
    发明公开
    MULTIPLE REGISTER MEMORY ACCESS INSTRUCTIONS, PROCESSORS, METHODS, AND SYSTEMS 审中-公开
    存储器访问命令，处理器，方法，并与多种寄存器的系统

    公开(公告)号：EP3014416A4

    公开(公告)日：2017-02-22

    申请号：EP14817022

    申请日：2014-06-26

    Applicant: INTEL CORP

    Inventor： HINTON GLENN ,  TOLL BRET ,  SINGHAL RONAK

    IPC: G06F9/06 ,  G06F9/30 ,  G06F12/08

    CPC classification number: G11C7/1036 ,  G06F9/30043 ,  G06F9/30109 ,  G06F9/30163

    Abstract: A processor includes N-bit registers and a decode unit to receive a multiple register memory access instruction. The multiple register memory access instruction is to indicate a memory location and a register. The processor includes a memory access unit coupled with the decode unit and with the N-bit registers. The memory access unit is to perform a multiple register memory access operation in response to the multiple register memory access instruction. The operation is to involve N-bit data, in each of the N-bit registers comprising the indicated register. The operation is also to involve different corresponding N-bit portions of an M×N-bit line of memory corresponding to the indicated memory location. A total number of bits of the N-bit data in the N-bit registers to be involved in the multiple register memory access operation is to amount to at least half of the M×N-bits of the line of memory.

    STACK FRAME CACHE
    8.
    发明专利
    STACK FRAME CACHE 未知

    公开(公告)号：HK57590A

    公开(公告)日：1990-08-10

    申请号：HK57590

    申请日：1990-08-02

    Applicant: INTEL CORP

    Inventor： MYERS GLENFORD J ,  LAI KONRAD ,  IMEI MICHAEL T ,  HINTON GLENN ,  RICHES ROBERT

    IPC: G06F9/42 ,  G06F9/30 ,  G06F9/40 ,  G06F9/46 ,  G06F12/08

    Abstract: A plurality of global registers are provided on the microprocessor chip. One of a global registers is a frame pointer register containing the current frame pointer, and the remainder of the global registers are available to a current process as general registers. A plurality of floating point registers are also provided for use by the current process in execution of floating point arithmetic operations. A register set pool made up of a plurality of register sets is provided, each register set being comprised of a number of local registers. When a call instruction is decoded, a register set of local registers from the register set pool is allocated to the called procedure, and the frame pointer register is initialized. When a return instruction is decoded, the register set is freed for allocation to another procedure called by a subsequent call instruction. If the register set pool is depleted a register set associated with a previous procedure is saved in the main memory, and that register set is allocated to the current procedure. The local registers in a register set associated with a procedure contain linkage information including a pointer to the previous frame and an instruction pointer, thus enabling most call and return instructions to execute without needing any references to off-chip memory.

    STACK FRAME CACHE ON A MICROPROCESSOR CHIP
    9.
    发明专利
    STACK FRAME CACHE ON A MICROPROCESSOR CHIP 未知

    公开(公告)号：GB2190521A

    公开(公告)日：1987-11-18

    申请号：GB8628175

    申请日：1986-11-25

    Applicant: INTEL CORP

    Inventor： MYERS GLENFORD J ,  LAI KONRAD ,  IMEL MICHAEL T ,  HINTON GLENN ,  RICHES ROBERT

    IPC: G06F9/42 ,  G06F9/30 ,  G06F9/40 ,  G06F9/46 ,  G06F12/08

    Abstract: A plurality of global registers are provided on the microprocessor chip. One of a global registers is a frame pointer register containing the current frame pointer, and the remainder of the global registers are available to a current process as general registers. A plurality of floating point registers are also provided for use by the current process in execution of floating point arithmetic operations. A register set pool made up of a plurality of register sets is provided, each register set being comprised of a number of local registers. When a call instruction is decoded, a register set of local registers from the register set pool is allocated to the called procedure, and the frame pointer register is initialized. When a return instruction is decoded, the register set is freed for allocation to another procedure called by a subsequent call instruction. If the register set pool is depleted a register set associated with a previous procedure is saved in the main memory, and that register set is allocated to the current procedure. The local registers in a register set associated with a procedure contain linkage information including a pointer to the previous frame and an instruction pointer, thus enabling most call and return instructions to execute without needing any references to off-chip memory.

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