公开(公告)号：US20200152555A1

公开(公告)日：2020-05-14

申请号：US16745920

申请日：2020-01-17

Applicant: J-Devices Corporation

Inventor： Masafumi SUZUHARA

IPC: H01L23/495 ,  H01L23/31 ,  H01L21/56 ,  H01L21/48

Abstract: A semiconductor package includes a die pad; a plurality of external connection terminals located around the die pad; a semiconductor chip located on a top surface of the die pad and electrically connected with the plurality of external connection terminals; and a sealing member covering the die pad, the plurality of external connection terminals and the semiconductor chip and exposing an outer terminal of each of the plurality of external connection terminals. A side surface of the outer terminal of each of the plurality of external connection terminals includes a first area, and the first area is plated.

公开(公告)号：US10529635B2

公开(公告)日：2020-01-07

申请号：US15493231

申请日：2017-04-21

Applicant: J-DEVICES CORPORATION

Inventor： Hisakazu Marutani ,  Minoru Kai ,  Kazuhiko Kitano

IPC: H01L23/31 ,  H01L21/56 ,  H01L21/82 ,  H01L23/544 ,  H01L23/00

Abstract: A manufacturing method of a semiconductor package includes locating a plurality of semiconductor packages on a substrate, forming a resin insulating layer covering the plurality of semiconductor devices, forming grooves, in the resin insulating layer, enclosing each of the plurality of semiconductor devices and reaching the substrate, and irradiating the substrate with laser light in positional correspondence with the grooves to separate the plurality of semiconductor devices from each other.

公开(公告)号：US10236231B2

公开(公告)日：2019-03-19

申请号：US15640071

申请日：2017-06-30

Applicant: J-DEVICES CORPORATION

Inventor： Takeshi Miyakoshi ,  Sumikazu Hosoyamada ,  Yoshikazu Kumagaya ,  Tomoshige Chikai ,  Shingo Nakamura ,  Hiroaki Matsubara ,  Shotaro Sakumoto

IPC: H01L23/495 ,  H01L23/00 ,  H01L23/31 ,  H01L23/467 ,  H01L23/473 ,  H01L21/56

Abstract: A semiconductor device includes a lead frame; a circuit board located on the lead frame; a power device that includes a switching element and is mounted on the circuit board via a bump located between the power device and the circuit board; and a heat releasing member connected to the power device. The circuit board may be a multi-layer wiring board. The circuit board may include a capacitor element, a resistor element, an inductor element, a diode element and a switching element.

公开(公告)号：US10134710B2

公开(公告)日：2018-11-20

申请号：US15422981

申请日：2017-02-02

Applicant: J-DEVICES CORPORATION

Inventor： Takeshi Miyakoshi ,  Sumikazu Hosoyamada ,  Yoshikazu Kumagaya ,  Tomoshige Chikai ,  Shingo Nakamura ,  Hiroaki Matsubara ,  Shotaro Sakumoto

IPC: H01L23/48 ,  H01L23/52 ,  H01L25/065 ,  H01L23/31

Abstract: A stacked semiconductor package in an embodiment includes a first semiconductor package including a first circuit board and a first semiconductor element mounted on the first circuit board; and a second semiconductor package including a second circuit board and a second semiconductor element mounted on the second circuit board, the second semiconductor package being stacked on the first semiconductor package. The first semiconductor package further includes a sealing resin sealing the first semiconductor element; a conductive layer located in contact with the sealing resin; and a thermal via connected to the conductive layer and located on the first circuit board.

公开(公告)号：US10090276B2

公开(公告)日：2018-10-02

申请号：US14944480

申请日：2015-11-18

Applicant: J-DEVICES CORPORATION

Inventor： Kiyoaki Hashimoto

IPC: H01L25/065 ,  H01L23/538 ,  H01L23/00 ,  H01L23/498 ,  H01L23/31

Abstract: A semiconductor package includes a first semiconductor device provided on a support substrate; a first encapsulation material covering the first semiconductor device; a first line provided on the first encapsulation material, the first line being connected with the first semiconductor device; an intermediate buffer layer covering the first line, and a second encapsulation material provided on the intermediate buffer layer. The first encapsulation material and the second encapsulation material are each formed of an insulating material different from an insulating material used to form the intermediate buffer layer. A second semiconductor device covered with the second encapsulation material may be provided on the intermediate buffer layer.

公开(公告)号：US20170358462A1

公开(公告)日：2017-12-14

申请号：US15621493

申请日：2017-06-13

Applicant: J-DEVICES CORPORATION

Inventor： Seita ARAKI ,  Kazuhiko KITANO

IPC: H01L21/56 ,  H01L23/00 ,  H01L21/78

CPC classification number: H01L21/561 ,  H01L21/56 ,  H01L21/78 ,  H01L23/3128 ,  H01L23/544 ,  H01L24/03 ,  H01L24/19 ,  H01L24/20 ,  H01L24/32 ,  H01L24/83 ,  H01L24/92 ,  H01L24/97 ,  H01L2223/54426 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/18 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/82039 ,  H01L2224/83132 ,  H01L2224/83138 ,  H01L2224/83192 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2924/1432 ,  H01L2924/1434 ,  H01L2924/1461 ,  H01L2924/3025 ,  H01L2924/351 ,  H01L2224/83

Abstract: A manufacturing method of a semiconductor package includes disposing one or more semiconductor devices on a base substrate, each of the one or more semiconductor devices having an external terminal; forming a frame on the base substrate, the frame surrounding the one or more semiconductor devices; and forming a resin insulating layer inside the frame, the resin insulating layer sealing the one or more semiconductor devices and the resin insulating layer including a resin insulating material; wherein a surface of each of the one or more semiconductor devices on which the external terminal is not provided faces the base substrate.

公开(公告)号：US20170338136A1

公开(公告)日：2017-11-23

申请号：US15600082

申请日：2017-05-19

Applicant: J-DEVICES CORPORATION

Inventor： Minoru KAI

IPC: H01L21/67 ,  H01L23/498 ,  H01L21/68 ,  H01L23/00 ,  H01L23/14

CPC classification number: H01L21/67132 ,  H01L21/67144 ,  H01L21/681 ,  H01L21/6838 ,  H01L23/147 ,  H01L23/49833 ,  H01L24/05 ,  H01L24/75

Abstract: A semiconductor manufacturing apparatus includes a stage connected to a vacuum generator to suction a semiconductor wafer including a plurality of semiconductor chips; a suction control unit connected to a connecting portion of the stage and the vacuum generator to control the connection of the stage and the vacuum generator; a pickup unit picking up each of the plurality of semiconductor chips; and a control unit controlling movement and rotation of the pickup unit and controlling the suction control unit; wherein the pickup unit moves the semiconductor chip from the stage to a mounting position of a supporting substrate and adherers the semiconductor chip by the control unit.

公开(公告)号：US20170317045A1

公开(公告)日：2017-11-02

申请号：US15481848

申请日：2017-04-07

Applicant: J-DEVICES CORPORATION

Inventor： Toshiyuki INAOKA ,  Atsuhiro URATSUJI

IPC: H01L23/00

CPC classification number: H01L24/27 ,  H01L24/04 ,  H01L24/11 ,  H01L24/19 ,  H01L24/20 ,  H01L24/64 ,  H01L24/97 ,  H01L2223/54426 ,  H01L2224/03001 ,  H01L2224/03618 ,  H01L2224/03632 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/8201 ,  H01L2224/82039 ,  H01L2224/83132 ,  H01L2224/83192 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2924/1432 ,  H01L2924/1434 ,  H01L2924/1461 ,  H01L2924/15159 ,  H01L2224/83

Abstract: A manufacturing method of a semiconductor package includes locating, on a substrate, a semiconductor device having an external terminal provided on a top surface thereof, forming a resin insulating layer covering the semiconductor device, forming an opening, exposing the external terminal, in the resin insulating layer, performing plasma treatment on a bottom surface of the opening, performing chemical treatment on the bottom surface of the opening after the plasma treatment, and forming a conductive body to be connected with the external terminal exposed in the opening.

公开(公告)号：US20170316996A1

公开(公告)日：2017-11-02

申请号：US15472387

申请日：2017-03-29

Applicant: J-DEVICES CORPORATION

Inventor： Yasuyuki TAKEHARA ,  Kazuhiko KITANO

IPC: H01L23/29 ,  H01L21/306 ,  H01L21/56 ,  H01L23/00

Abstract: A semiconductor package includes a substrate having at least one recessed portion, a semiconductor device located on a surface of the substrate, the surface having the at least one recessed portion, and a resin insulating layer covering the semiconductor device.

公开(公告)号：US20170263537A1

公开(公告)日：2017-09-14

申请号：US15446426

申请日：2017-03-01

Applicant: J-DEVICES CORPORATION

Inventor： Masafumi Suzuhara

IPC: H01L23/495 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L23/49524 ,  H01L21/4825 ,  H01L21/4842 ,  H01L21/56 ,  H01L23/3107 ,  H01L23/3142 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/49565 ,  H01L23/49582

Abstract: A semiconductor package includes a die pad; a plurality of external connection terminals located around the die pad; a semiconductor chip located on a top surface of the die pad and electrically connected with the plurality of external connection terminals; and a sealing member covering the die pad, the plurality of external connection terminals and the semiconductor chip and exposing an outer terminal of each of the plurality of external connection terminals. A side surface of the outer terminal of each of the plurality of external connection terminals includes a first area, and the first area is plated.