公开(公告)号：GB9425589D0

公开(公告)日：1995-02-15

申请号：GB9425589

申请日：1994-12-19

Applicant: KOREA ELECTRONICS TELECOMM ,  KOREA TELECOMMUNICATION

IPC: H01L21/331 ,  H01L21/762

Abstract: Disclosed is a method of fabricating an SOI substrate, comprising the steps of forming a first insulating layer on a single crystal silicon substrate; patterning the first insulating layer to form an opening; growing a single crystal silicon in the opening to form active and inactive regions; polishing the active region 31 as the first insulating layer as a polishing stopper to form a planarized surface; depositing a second insulating layer on the planarized surface; bonding a bonding substrate to the second insulating layer; and polishing the silicon substrate using the first insulating layer as a stopper up to a surface of the active region. By the method, a stray capacitance occurring between an SOI substrate and a metal wiring portion formed thereon can be significantly reduced owing to a relatively thick insulating layer therebetween, and a parasitic capacitance can be eliminated owing to an insulating layer interposed between a bonding substrate and an active region to be used as a buried collector.

公开(公告)号：PT101037A

公开(公告)日：1994-07-29

申请号：PT10103792

申请日：1992-11-05

Applicant: KOREA TELECOMMUNICATION

Inventor： LEE CHONG RAK ,  PARK YONG KYU

IPC: G10L13/04 ,  G10L13/06 ,  G10L19/00 ,  G10L21/04 ,  G10L25/90 ,  H04B

公开(公告)号：CA2115842A1

公开(公告)日：1994-01-26

申请号：CA2115842

申请日：1993-06-18

Applicant: KOREA TELECOMMUNICATION

Inventor： KIM EUN H ,  JIN BYUNG W ,  JOO WOON Y ,  YOON JE-ONG N

IPC: H04M17/00 ,  H04M3/24 ,  H04M17/02

Abstract: A coin/credit operated public telephone is capable of making local, toll, and international calls using coins, credit card, or IC card and also of making a voice announcement regarding its operation method to the caller through a handset (1). Moreover, it provides graphic/character information through the LCD (10) and can transmit fault status that has been detected as a result of a highly reliable self-diagnosis carried out by receiving control signals from a remotely located central management system.

公开(公告)号：ATA144692A

公开(公告)日：1993-12-15

申请号：AT144692

申请日：1992-07-15

Applicant: KOREA TELECOMMUNICATION

IPC: G06G7/163 ,  G06N3/063 ,  H03F3/16 ,  G06G7/60 ,  G06G7/16

Abstract: A MOSFET controlling multiplier for obtaining the precise function of the operational multiplication by offsetting the offset voltage of MOSFET to remove the non-linear current of MOSFET, utilizing symmetrical voltage sources and a current mirror circuit is disclosed. The MOSFET controlling multiplier utilizes a MOSFET linear means for linearly varying the output current I to a node A in accordance with an input voltage from an input voltage source Vg and a symmetrical input voltage from voltage sources Vx and -Vx. The input voltage from the input voltage source Vg is operatively associated with the symmetrical input voltage from the voltage sources Vx and -Vx. An impedance element Z outputs a voltage Vo, with the impedance element Z being connected to the node A of the MOSFET linear means and the ground.

公开(公告)号：MC2322A1

公开(公告)日：1993-10-25

申请号：MC2230

申请日：1992-06-12

Applicant: KOREA TELECOMMUNICATION

Inventor： M IL SONG HAN

IPC: G06G7/163 ,  G06N3/063 ,  H03F3/16 ,  G06F ,  H03B ,  H03K

Abstract: A MOSFET controlling multiplier for obtaining the precise function of the operational multiplication by offsetting the offset voltage of MOSFET to remove the non-linear current of MOSFET, utilizing symmetrical voltage sources and a current mirror circuit is disclosed. The MOSFET controlling multiplier utilizes a MOSFET linear means for linearly varying the output current I to a node A in accordance with an input voltage from an input voltage source Vg and a symmetrical input voltage from voltage sources Vx and -Vx. The input voltage from the input voltage source Vg is operatively associated with the symmetrical input voltage from the voltage sources Vx and -Vx. An impedance element Z outputs a voltage Vo, with the impedance element Z being connected to the node A of the MOSFET linear means and the ground.

公开(公告)号：ES2040659A2

公开(公告)日：1993-10-16

申请号：ES9201484

申请日：1992-07-16

Applicant: KOREA TELECOMMUNICATION

Inventor： IL SONG HAN

IPC: G06G7/163 ,  G06N3/063 ,  H03F3/16 ,  G06G7/02

Abstract: MULTIPLICADOR DE CONTROL CON MOSFETS. ESTA DESTINADO A LA OBTENCION DE LA FUNCION PRECISA DE LA MULTIPLICACION OPERACIONAL POR DESPLAZAMIENTO DE LA TENSION DE DESPLAZAMIENTO DE LOS MOSFETS PARA ELIMINAR SU INTENSIDAD NO LINEAL. UTILIZA FUENTES DE TENSION SIMETRICA, UN CIRCUITO ESPECULAR DE INTENSIDAD Y MEDIOS LINEALES DE MOSFET PARA HACER VARIAR LINEALMENTE LA INTENSIDAD DE SALIDA HACIA UN NODO, DE ACUERDO CON UNA TENSION DE ENTRADA PROCEDENTE DE UNA FUENTE VG Y UNA TENSION SIMETRICA DE ENTRADA PROCEDENTE DE FUENTES VX Y -VX. LA TENSION DE ENTRADA DE LA FUENTE VG ESTA ASOCIADA OPERATIVAMENTE CON LA TENSION SIMETRICA DE ENTRADA PROCEDENTE DE LAS FUENTES VX Y -VX. UN ELEMENTO DE IMPEDANCIA PRODUCE UNA TENSION VO, ESTANDO CONECTADO EL ELEMENTO DE IMPEDANCIA AL NODO DE LOS MEDIOS LINEALES DE MOSFET Y LA MASA. APLICABLE, PARTICULARMENTE, PARA OBTENER HIBRIDOS ANALOGICO-DIGITALES DE UNA SINAPSIS NEURAL ARTIFICIAL.

公开(公告)号：GB2233177B

公开(公告)日：1993-06-16

申请号：GB9010055

申请日：1990-05-04

Applicant: KOREA ELECTRONICS TELECOMM ,  KOREA TELECOMMUNICATION

Inventor： SHIN DONG KWAN

IPC: H03L7/06 ,  H03K7/06 ,  H03L7/081 ,  H03L7/089 ,  H04J3/06 ,  H04L7/00 ,  H04L7/033 ,  H04L25/40

Abstract: This invention provides a digital auto-phase-controlled retiming circuit which automatically locates the retiming clock phase in the center of input data eye pattern by detesting the phase difference between retiming clock and data and tracking adoptively the mutual phase variation in a case that the mutual phase difference between data and retiming clock is uncertain and changes according to time in digital transmission and/or digital signal processing systems.

公开(公告)号：ES2037623A2

公开(公告)日：1993-06-16

申请号：ES9202232

申请日：1992-11-05

Applicant: KOREA TELECOMMUNICATION

Inventor： RAK LEE CHONG ,  KYU PARK YONG

IPC: G10L13/04 ,  G10L13/06 ,  G10L19/00 ,  G10L21/04 ,  G10L25/90 ,  G10L5/04

Abstract: METODO Y DISPOSITIVO DE SINTESIS DEL HABLA. LA INVENCION PERTENECE AL CAMPO DE LA SINTESIS DEL HABLA Y UTILIZA UN SISTEMA PERIODICO DE DESCOMPOSICION DE FORMAS DE ONDA Y DE REUBICACION DE ESTAS, EL CUAL SISTEMA INCLUYE UN METODO DE CODIFICACION EN QUE SE DESCOMPONEN SEÑALES DE INTERVALOS DE SONIDO SONORO DEL HABLA ORIGINAL PARA DAR TRENES DE ONDAS QUE CORRESPONDEN CADA UNO A UNA FORMA DE ONDA DEL HABLA, PARA UN PERIODO CONSTITUIDO POR CADA PULSO GLOTAL, Y LOS TRENES DE ONDAS SON RESPECTIVAMENTE CODIFICADOS Y MEMORIZADOS. SE TRATA DE UNA TECNOLOGIA POR MEDIO DE LA CUAL LOS TRENES DE ONDAS MAS PROXIMOS A LAS POSICIONES EN LAS QUE HAN DE UBICARSE LOS TRENES DE ONDAS SON SELECCIONADOS DE ENTRE LOS TRENES DE ONDAS MEMORIZADOS Y SON DESCODIFICADOS Y SUPERPUESTOS. LA INVENCION ES APLICABLE A LA SINTESIS DE VOZ HUMANA A PARTIR DE TEXTO ENTRADO POR ORDENADOR, Y SIMILARES.

公开(公告)号：NL9201212A

公开(公告)日：1993-06-01

申请号：NL9201212

申请日：1992-07-07

Applicant: KOREA TELECOMMUNICATION

IPC: G06G7/163 ,  G06N3/063 ,  H03F3/16

Abstract: A MOSFET analog multiplier with a variable resistive MOSFET linear means for linearly varying output current I depending upon a symmetrical input voltage from voltage sources V2 and -V2 and an input voltage from an input voltage source V1 operatively associated with the symmetrical input voltage from the voltage source V2 and -V2, with the variable resistive MOSFET linear means having a node A to output the varied output current I therethrough is disclosed. An operational amplifying unit for amplifying the linearly varied output current I and which includes an operational amplifier U with an inverting input terminal connected to the node A of the MOSFET linear means, a non-inverting input terminal connected to ground, and an output terminal. The operational amplifying unit further includes a feedback element Z connected between the inverting input terminal and the output terminal of the operational amplifier U, where in use the output terminal outputs a voltage Vo.

公开(公告)号：DE4222844A1

公开(公告)日：1993-05-06

申请号：DE4222844

申请日：1992-07-11

Applicant: KOREA TELECOMMUNICATION AUTHORITY, SEOUL/SOUL, KR

Inventor： VERZICHT DES ERFINDERS AUF NENNUNG

IPC: G06G7/163 ,  G06N3/063 ,  H03F3/16

Abstract: A MOSFET analog multiplier with a variable resistive MOSFET linear means for linearly varying output current I depending upon a symmetrical input voltage from voltage sources V2 and -V2 and an input voltage from an input voltage source V1 operatively associated with the symmetrical input voltage from the voltage source V2 and -V2, with the variable resistive MOSFET linear means having a node A to output the varied output current I therethrough is disclosed. An operational amplifying unit for amplifying the linearly varied output current I and which includes an operational amplifier U with an inverting input terminal connected to the node A of the MOSFET linear means, a non-inverting input terminal connected to ground, and an output terminal. The operational amplifying unit further includes a feedback element Z connected between the inverting input terminal and the output terminal of the operational amplifier U, where in use the output terminal outputs a voltage Vo.