公开(公告)号：EP1056192A2

公开(公告)日：2000-11-29

申请号：EP00116212.2

申请日：1996-06-24

Applicant: UNIVERSITY OF BRISTOL ,  STMicroelectronics Limited

Inventor： Beach, Mark Anthony ,  Mattos, Philip Gerad

IPC: H03D3/00

CPC classification number: H03B25/00 ,  H03D3/006

Abstract: A fixed frequency dual downconversion receiver, comprises: an analog first downconversion and IF filter stage; means for one-bit coding of the downconverted signal; and means for second downconversion by digital subsampling. The receiver is particularly suitable for use in GPS applications.

Abstract translation: 固定频率双下变频接收机，包括：模拟的第一下变频和IF滤波器级; 用于下变频信号的一位编码的装置; 以及通过数字子采样进行第二次下变频的装置。 接收器特别适用于GPS应用。

公开(公告)号：EP1041390A1

公开(公告)日：2000-10-04

申请号：EP00301289.5

申请日：2000-02-18

Applicant: STMicroelectronics Limited

Inventor： Warren, Robert

IPC: G01R31/3185

CPC classification number: G01R31/318552

Abstract: An integrated circuit comprises a serial data input pin and a serial data output pin, on-chip functional circuitry and test logic, a test access port controller connected to effect communication of serial data across the chip boundary via said input and output pins, the test access port controller being connectable to the test logic in a first mode of operation to effect communication of serial test data off-chip, a data adaptor which is connectable to the input and output pins via the test access port controller in a second mode of operation, wherein the data adaptor comprises a first interface for communicating data in the form of serial bits to and from said test access port controller under the control of a first clock signal and a second interface for communicating data in the form of successive sets of parallel data and control signals to and from said on-chip functional circuitry under the control of a second clock signal generated independently of said first clock signal, and wherein said data adaptor comprises data storage means for holding data received in the data adaptor to take into account differences between the first and second clock signals.

Abstract translation: 集成电路包括串行数据输入引脚和串行数据输出引脚，片上功能电路和测试逻辑，连接的测试访问端口控制器，用于通过所述输入和输出引脚在芯片边界上实现串行数据的通信，测试 访问端口控制器可以在第一操作模式下连接到测试逻辑，以实现片外串行测试数据的通信，数据适配器可以通过第二操作模式经由测试访问端口控制器连接到输入和输出引脚 ，其中所述数据适配器包括用于在第一时钟信号的控制下以串行比特的形式传送来自所述测试访问端口控制器的数据的第一接口和用于以连续的并行数据集合的形式传送数据的第二接口 以及在独立于所述第一时钟信号产生的第二时钟信号的控制下控制来自所述片上功能电路的信号，以及w 这里所述数据适配器包括用于保存数据适配器中接收的数据以考虑第一和第二时钟信号之间的差异的数据存储装置。

公开(公告)号：EP0560598B1

公开(公告)日：2000-07-26

申请号：EP93301833.5

申请日：1993-03-10

Applicant: STMicroelectronics Limited

Inventor： Stansfield, Anthony Ian ,  Barnaby, Catherine Louise ,  Gammack, Richard John ,  Shepherd, Roger Mark

IPC: G06F12/08 ,  G06F12/10

CPC classification number: G06F12/1063

公开(公告)号：EP1016995A1

公开(公告)日：2000-07-05

申请号：EP99308975.4

申请日：1999-11-11

Applicant: STMicroelectronics Limited

Inventor： Hill, Mark ,  Sturges, Andrew ,  Agterkamp, Hendrik-Jan

IPC: G06F17/50

CPC classification number: G06F17/5022

Abstract: A computer is operated to generate electronic data defining a system model by loading into the computer a class definition defining instructions which are processed by the system, the definition including a set of functional methods to which the instruction is subjected by the system and a set of locations for members representing the instruction. A model execution program is then executed on the computer which calls the class definition for each instruction, invokes one of the functional methods and loads the locations of the entry with state information depending on the functional method to create a functional component. The functional component is loaded into memory and the state information of the functional component modified in dependence on a subsequently invoked functional method by the model execution program.
The class definitions may be one of the members and may be the address of the instruction in a memory of the processor being modelled, a record of any loops caused by the instruction, the opcode of the instruction describing the effect of the instruction when executed, a pointer to a description of the effect of the instruction when executed or an array of operands including input and output operand values for the instructions.

Abstract translation: 计算机被操作以通过将定义由系统处理的指令的类定义加载到计算机中来定义系统模型的电子数据，该定义包括系统对指令进行的一组功能方法，以及一组 代表指示的成员的地点。 然后在调用每个指令的类定义的计算机上执行模型执行程序，根据功能方法调用其中一个功能方法并加载具有状态信息的条目的位置以创建功能组件。 功能组件被加载到存储器中，并且功能组件的状态信息根据模型执行程序随后调用的功能方法进行修改。 类定义可以是成员之一，并且可以是被建模的处理器的存储器中的指令的地址，由指令引起的任何循环的记录，描述执行时指令的影响的指令的操作码， 指向执行时指令效果的指针或包含指令的输入和输出操作数值的操作数组。

公开(公告)号：EP0713167B1

公开(公告)日：2000-05-31

申请号：EP95308091.8

申请日：1995-11-13

Applicant: STMicroelectronics Limited

Inventor： Whitfield, Colin

IPC: G05F3/24 ,  G11C5/14

CPC classification number: G11C5/143 ,  G05F3/24

公开(公告)号：EP0698889B1

公开(公告)日：2000-05-31

申请号：EP95305827.8

申请日：1995-08-21

Applicant: STMicroelectronics Limited

Inventor： Whitfield, Colin

IPC: G11C16/06 ,  G01R31/27

CPC classification number: G11C16/24 ,  G01R31/275 ,  G11C16/30

公开(公告)号：EP0698888B1

公开(公告)日：2000-05-31

申请号：EP95305819.5

申请日：1995-08-21

Applicant: STMicroelectronics Limited

Inventor： Whitfield, Colin

IPC: G11C16/06

CPC classification number: G11C16/16

公开(公告)号：EP0971502A2

公开(公告)日：2000-01-12

申请号：EP99203397.7

申请日：1991-02-20

Applicant: STMicroelectronics Limited

Inventor： Simpson, Robert J.

IPC: H04L1/00

CPC classification number: H04L1/0063 ,  H04L1/0057 ,  H04L1/0083 ,  H04L7/0008 ,  H04L7/0037 ,  H04L7/0041 ,  H04L7/033 ,  H04L7/048

Abstract: A communication interface for interconnecting a computer with at least one other device has a link output circuit and a link input circuit. A link output on one device is connected to a link input on another device by a data line 25 and a parallel strobe line 26. Data is transmitted on the data line 25 in serial bit strings forming a succession of tokens of predetermined lengths. Signal transitions are provided on the parallel strobe line 26 where no signal transition occurs on the data line 25. Each token includes a bit indicating the length of the token and a parity bit providing a check on bits in a preceding token.

公开(公告)号：EP0969395A1

公开(公告)日：2000-01-05

申请号：EP99304713.3

申请日：1999-06-16

Applicant: STMicroelectronics Limited

Inventor： Panesar, Gajinder

IPC: G06F17/50

CPC classification number: G06F17/5022 ,  G06F17/5045 ,  G06F2217/68

Abstract: A computer system for simulating an ASP comprises first processor means including execution means for simulating a functional model in a high level language and output means for outputting the state of the functional model at the end of a predetermined simulation phase, means for converting the functional model, including its state at the end of the predetermined simulation phase, into a simulation language for simulating the ASP at circuit level, and second processor means arranged to execute the simulation language to simulate the ASP at circuit level for a subsequent simulation phase.

Abstract translation: 一种用于模拟ASP的计算机系统包括第一处理器装置，包括用于模拟高级语言的功能模型的执行装置和用于在预定模拟阶段结束时输出功能模型的状态的输出装置，用于将功能模型 （包括其在预定模拟阶段结束时的状态）转换成用于在电路级模拟ASP的仿真语言，以及第二处理器装置，被配置为执行模拟语言以在后续仿真阶段的电路级模拟ASP。

公开(公告)号：EP0953915A1

公开(公告)日：1999-11-03

申请号：EP99303254.9

申请日：1999-04-27

Applicant: STMicroelectronics Limited

Inventor： Jones, Andrew Michael ,  May, Michael David

IPC: G06F13/38

CPC classification number: G06F13/385

Abstract: A chip (11) with an address and data path (15) interconnecting at least one CPU (12) with another module (14) and an external communication port (30), the CPU generating event packets and memory access packets and the module (14) generating event packets, the packets being distributed in parallel format on the path 15 and the external communication port (30) including circuitry to reduce the parallel format of each packet to a more serial format for off-chip communication.

Abstract translation: 具有将至少一个CPU（12）与另一模块（14）和外部通信端口（30）互连的地址和数据路径（15）的芯片（11），所述CPU生成事件分组和存储器访问分组以及所述模块 14）生成事件分组，分组以并行格式分布在路径15上，外部通信端口（30）包括电路，以将每个分组的并行格式减小到更多的串行格式用于片外通信。