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    Interrupt and control packets for a microcomputer
    4.
    发明公开
    Interrupt and control packets for a microcomputer 审中-公开
    Unterbrechungs- / Steuerungspaketefüreinen Mikrorechner

    公开(公告)号：EP0959412A1

    公开(公告)日：1999-11-24

    申请号：EP99303251.5

    申请日：1999-04-27

    Applicant: STMicroelectronics Limited

    Inventor： Jones, Andrew Michael ,  May, Michael David

    IPC: G06F13/38

    CPC classification number: G06F13/385

    Abstract: An integrated circuit chip (11) has an address and data path (15) interconnecting at least one CPU (12) with a different module (15), the CPU and module each having event logic (8,44) to generate event request packets of two types, each having a destination address, one type being a control packet to which a destination device must respond on receipt and the other type including a priority indicator such that the destination device can selectively respond depending on the priority detected.

    Abstract translation: 集成电路芯片（11）具有将至少一个CPU（12）与不同模块（15）互连的地址和数据路径（15），所述CPU和模块各自具有事件逻辑（8,44）以生成事件请求分组 每种类型具有目的地地址，一种类型是目的地设备在接收时必须响应的控制分组，另一种类型包括优先级指示符，使得目的地设备可以根据检测到的优先级选择性地进行响应。

    Packet distribution in a microcomputer
    7.
    发明公开
    Packet distribution in a microcomputer 有权
    在einem Mikrorechner的Paketverteilung

    公开(公告)号：EP0959411A1

    公开(公告)日：1999-11-24

    申请号：EP99303253.1

    申请日：1999-04-27

    Applicant: STMicroelectronics Limited

    Inventor： Jones, Andrew Michael ,  May, Michael David

    IPC: G06F13/24

    CPC classification number: G06F13/24

    Abstract: An integrated circuit device (11) with an address and data path (15) interconnects a CPU (12) with at least one module (14) and a memory interface (32), the module (14) having circuitry (8) to generate an event request packet and the CPU having event logic (44) to decode the packet as well as circuitry to generate addressed memory access packets, the same address and data path (15) being used for the distribution of event request packets and memory access packets.

    Abstract translation: 具有地址和数据路径（15）的集成电路设备（11）将CPU（12）与至少一个模块（14）和存储器接口（32）互连，所述模块（14）具有电路（8）以产生 事件请求分组和具有用于解码分组的事件逻辑（44）的CPU以及用于生成寻址的存储器访问分组的电路的CPU，用于分发事件请求分组和存储器访问分组的相同的地址和数据路径（15） 。

    Microcomputer chips with interconnected address and data paths
    8.
    发明公开
    Microcomputer chips with interconnected address and data paths 审中-公开
    Mikrorechner-Chip mit untereinander verbundenen Address- und Datenwegen

    公开(公告)号：EP0953916A1

    公开(公告)日：1999-11-03

    申请号：EP99303250.7

    申请日：1999-04-27

    Applicant: STMicroelectronics Limited

    Inventor： Jones, Andrew Michael ,  May, Michael David

    IPC: G06F13/40

    CPC classification number: G06F13/26

    Abstract: A computer system comprises interconnected chips (11) each having an on-chip address and data path (15), a CPU (12) arranged to send and receive addressed bit packets on the path and modules (14) with event circuitry (8) to generate addressed event request packets for distribution on the path (15), the two chips being interconnected through respective external ports (30) so that locations on each of the paths (15) form part of a common address space accessible from either chip.

    Abstract translation: 计算机系统包括每个具有片上地址和数据路径（15）的互连芯片（11），布置成在路径上发送和接收寻址的位分组的CPU（12）以及具有事件电路（8）的模块（14） 为了生成用于在路径（15）上分配的寻址事件请求分组，两个芯片通过相应的外部端口（30）互连，使得每个路径（15）上的位置形成可从任一芯片访问的公共地址空间的一部分。

    Microcomputer with bit packets for interrupts, control and memory access
    9.
    发明公开
    Microcomputer with bit packets for interrupts, control and memory access 审中-公开
    Mikrorechner mit Paketen von BitfürUnterbrechungen，Steuerung und Speicherzugriff

    公开(公告)号：EP0953914A1

    公开(公告)日：1999-11-03

    申请号：EP99303252.3

    申请日：1999-04-27

    Applicant: STMicroelectronics Limited

    Inventor： Jones, Andrew Michael ,  May, Michael David

    IPC: G06F13/38

    CPC classification number: G06F13/385

    Abstract: A computer system comprises one or more chips (11) each having at least one CPU (12) interconnected by an address and data path (15) to a plurality of modules (14) and an external communication port (30) the address and data path (15) distributing between devices bit packets comprising memory access packets, event packets for prioritised interrupts and control packets for control commands each of the packets being formed selectively in response to both software and hardware circuitry and having a common format including destination address and decodable function.

    Abstract translation: 计算机系统包括一个或多个芯片（11），每个芯片具有通过地址和数据路径（15）与多个模块（14）和外部通信端口（30）互连的至少一个CPU（12），地址和数据 路径（15）在设备之间分配包括存储器访问分组的比特分组，用于优先中断的事件分组和用于控制命令的控制分组，每个分组响应于软件和硬件电路选择性地形成，并具有包括目的地地址和可解码的共同格式 功能。

    Method and device to simulate interruptions for the emulation of a processor
    10.
    发明公开
    Method and device to simulate interruptions for the emulation of a processor 有权
    装置和方法用于模拟中断在处理器的仿真

    公开(公告)号：EP0942374A1

    公开(公告)日：1999-09-15

    申请号：EP99301876.1

    申请日：1999-03-11

    Applicant: STMicroelectronics Limited

    Inventor： Edwards, David Alan ,  Jones, Andrew Michael

    IPC: G06F11/00 ,  G06F12/02

    CPC classification number: G06F11/3664 ,  G06F11/261 ,  G06F11/3648

    Abstract: A computer system comprising a microprocessor on a single integrated circuit chip connected to an external computer device and at least one other device; the integrated circuit chip having: an on-chip CPU with a plurality of registers; a communication bus for providing a parallel communication path between the CPU and a first memory local to the CPU; and an external communication port connected to the communication bus, the port having an internal connection to the bus of an internal parallel signal format and an external connection to the external computer device of an external format less parallel than the said internal format, the port forming part of the memory address space of the CPU from which instructions may be fetched, whereby: the port may be addressed by execution of an instruction by the CPU; and the external computer device may send to the integrated circuit chip an interrupt signal simulating an interrupt signal from the other device.

    Abstract translation: 一种计算机系统，包括连接到外部计算机装置和至少一个其他设备在单个集成电路芯片上的微处理器; 具有集成电路芯片：一个片上CPU与寄存器的多元性; 用于提供所述CPU和第一本地存储器到CPU之间的并行通信路径的通信总线; 并连接到通信总线外部通信端口，具有一个内部并行信号格式的，并为外部格式的小于所述内部格式平行的外部计算机装置的外部连接的总线内部连接的端口，该端口形成 CPU的存储器地址空间从哪个指令可以被取出，由此的一部分：该端口可以通过由CPU的指令的执行来解决; 和外部计算机设备可以被发送到所述集成电路芯片中断信号模拟到从其他设备中断信号。

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