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    Microcomputer with interrupt packets
    2.
    发明公开
    Microcomputer with interrupt packets 审中-公开
    Mikrorechner mit Unterbrechungspaketen

    公开(公告)号：EP0953913A1

    公开(公告)日：1999-11-03

    申请号：EP99303255.6

    申请日：1999-04-27

    Applicant: STMicroelectronics Limited

    Inventor： Jones, Andrew Michael ,  May, Michael David

    IPC: G06F13/24

    CPC classification number: G06F13/24

    Abstract: An integrated circuit device (11) has an address and data path (15) interconnecting a CPU (12) with modules (14) the modules having event logic (8) to generate an event request packet having a destination address and the CPU decoding the packet to selectively respond to the request of the packet depending on the priority of the event.

    Abstract translation: 集成电路装置（11）具有将CPU（12）与具有事件逻辑（8）的模块（14）互连的地址和数据路径（15），以生成具有目的地地址的事件请求分组，并且CPU对 分组以根据事件的优先级选择性地响应分组的请求。

    Microcomputer with packet translation for event packets and memory access packets
    4.
    发明公开
    Microcomputer with packet translation for event packets and memory access packets 审中-公开
    Mikrorechner mitPaketübersetzungfürEreignispakete und Speicherzugriffpakete

    公开(公告)号：EP0953915A1

    公开(公告)日：1999-11-03

    申请号：EP99303254.9

    申请日：1999-04-27

    Applicant: STMicroelectronics Limited

    Inventor： Jones, Andrew Michael ,  May, Michael David

    IPC: G06F13/38

    CPC classification number: G06F13/385

    Abstract: A chip (11) with an address and data path (15) interconnecting at least one CPU (12) with another module (14) and an external communication port (30), the CPU generating event packets and memory access packets and the module (14) generating event packets, the packets being distributed in parallel format on the path 15 and the external communication port (30) including circuitry to reduce the parallel format of each packet to a more serial format for off-chip communication.

    Abstract translation: 具有将至少一个CPU（12）与另一模块（14）和外部通信端口（30）互连的地址和数据路径（15）的芯片（11），所述CPU生成事件分组和存储器访问分组以及所述模块 14）生成事件分组，分组以并行格式分布在路径15上，外部通信端口（30）包括电路，以将每个分组的并行格式减小到更多的串行格式用于片外通信。

    Interrupt and control packets for a microcomputer
    7.
    发明公开
    Interrupt and control packets for a microcomputer 审中-公开
    Unterbrechungs- / Steuerungspaketefüreinen Mikrorechner

    公开(公告)号：EP0959412A1

    公开(公告)日：1999-11-24

    申请号：EP99303251.5

    申请日：1999-04-27

    Applicant: STMicroelectronics Limited

    Inventor： Jones, Andrew Michael ,  May, Michael David

    IPC: G06F13/38

    CPC classification number: G06F13/385

    Abstract: An integrated circuit chip (11) has an address and data path (15) interconnecting at least one CPU (12) with a different module (15), the CPU and module each having event logic (8,44) to generate event request packets of two types, each having a destination address, one type being a control packet to which a destination device must respond on receipt and the other type including a priority indicator such that the destination device can selectively respond depending on the priority detected.

    Abstract translation: 集成电路芯片（11）具有将至少一个CPU（12）与不同模块（15）互连的地址和数据路径（15），所述CPU和模块各自具有事件逻辑（8,44）以生成事件请求分组 每种类型具有目的地地址，一种类型是目的地设备在接收时必须响应的控制分组，另一种类型包括优先级指示符，使得目的地设备可以根据检测到的优先级选择性地进行响应。

    Packet distribution in a microcomputer
    9.
    发明公开
    Packet distribution in a microcomputer 有权
    在einem Mikrorechner的Paketverteilung

    公开(公告)号：EP0959411A1

    公开(公告)日：1999-11-24

    申请号：EP99303253.1

    申请日：1999-04-27

    Applicant: STMicroelectronics Limited

    Inventor： Jones, Andrew Michael ,  May, Michael David

    IPC: G06F13/24

    CPC classification number: G06F13/24

    Abstract: An integrated circuit device (11) with an address and data path (15) interconnects a CPU (12) with at least one module (14) and a memory interface (32), the module (14) having circuitry (8) to generate an event request packet and the CPU having event logic (44) to decode the packet as well as circuitry to generate addressed memory access packets, the same address and data path (15) being used for the distribution of event request packets and memory access packets.

    Abstract translation: 具有地址和数据路径（15）的集成电路设备（11）将CPU（12）与至少一个模块（14）和存储器接口（32）互连，所述模块（14）具有电路（8）以产生 事件请求分组和具有用于解码分组的事件逻辑（44）的CPU以及用于生成寻址的存储器访问分组的电路的CPU，用于分发事件请求分组和存储器访问分组的相同的地址和数据路径（15） 。

    Microcomputer chips with interconnected address and data paths
    10.
    发明公开
    Microcomputer chips with interconnected address and data paths 审中-公开
    Mikrorechner-Chip mit untereinander verbundenen Address- und Datenwegen

    公开(公告)号：EP0953916A1

    公开(公告)日：1999-11-03

    申请号：EP99303250.7

    申请日：1999-04-27

    Applicant: STMicroelectronics Limited

    Inventor： Jones, Andrew Michael ,  May, Michael David

    IPC: G06F13/40

    CPC classification number: G06F13/26

    Abstract: A computer system comprises interconnected chips (11) each having an on-chip address and data path (15), a CPU (12) arranged to send and receive addressed bit packets on the path and modules (14) with event circuitry (8) to generate addressed event request packets for distribution on the path (15), the two chips being interconnected through respective external ports (30) so that locations on each of the paths (15) form part of a common address space accessible from either chip.

    Abstract translation: 计算机系统包括每个具有片上地址和数据路径（15）的互连芯片（11），布置成在路径上发送和接收寻址的位分组的CPU（12）以及具有事件电路（8）的模块（14） 为了生成用于在路径（15）上分配的寻址事件请求分组，两个芯片通过相应的外部端口（30）互连，使得每个路径（15）上的位置形成可从任一芯片访问的公共地址空间的一部分。

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