公开(公告)号：WO1996024234A1

公开(公告)日：1996-08-08

申请号：PCT/US1996000059

申请日：1996-01-16

Applicant: INTEL CORPORATION

Inventor： INTEL CORPORATION ,  AGATSTEIN, Louis, W. ,  NEAL, James, R.

IPC: H05K05/00

CPC classification number: H05K1/141 ,  G06F1/26 ,  H05K1/0262 ,  H05K1/0286 ,  H05K1/18 ,  H05K3/366 ,  H05K2201/10189 ,  H05K2201/10196

Abstract: An apparatus for regulating voltage and power in a computer system is disclosed. The voltage and power regulation is performed by voltage regulation circuitry on a voltage regulator module (200). The voltage regulator module (200) is a detachable unit which interfaces with the motherboard (340) through a socket connector (335). The socket connector (335) has a fixed pin definition which allows a variety of voltage regulator modules (200) programmed to regulate voltages and power at different levels to be implemented on the motherboard (340).

Abstract translation: 公开了一种用于调节计算机系统中的电压和功率的装置。 电压和功率调节由电压调节器模块（200）上的电压调节电路执行。 电压调节器模块（200）是通过插座连接器（335）与母板（340）接口的可拆卸单元。 插座连接器（335）具有固定的引脚定义，其允许编程为调节在主板（340）上实现的不同级别的电压和功率的各种电压调节器模块（200）。

公开(公告)号：WO1996021276A1

公开(公告)日：1996-07-11

申请号：PCT/US1995016881

申请日：1995-12-28

Applicant: INTEL CORPORATION

Inventor： INTEL CORPORATION ,  TAYLOR, Gregory, F. ,  SMITH, Jeffrey, E.

IPC: H03K19/00

CPC classification number: H03K3/013 ,  H03K3/0375

Abstract: A method and apparatus for providing a clock noise filter are described. The clock noise filter uses a transparent latch (10) which has a trigger input and a data input. The data input is coupled to receive an input clock signal (CLOCK) to be filtered. The output of the latch is the filtered clock signal (FCLOCK). The filtered clock signal has a logic state which corresponds to a logic state of the input clock signal when a trigger input has a first logic state, and the filtered clock signal is inhibited from changing logic state when the trigger input has a second logic state.

Abstract translation: 描述了一种用于提供时钟噪声滤波器的方法和装置。 时钟噪声滤波器使用具有触发输入和数据输入的透明锁存器（10）。 数据输入被耦合以接收要过滤的输入时钟信号（CLOCK）。 锁存器的输出是经过滤波的时钟信号（FCLOCK）。 当触发输入具有第一逻辑状态时，经滤波的时钟信号具有对应于输入时钟信号的逻辑状态的逻辑状态，并且当触发输入具有第二逻辑状态时，滤波后的时钟信号被禁止改变逻辑状态。

公开(公告)号：WO1996021226A1

公开(公告)日：1996-07-11

申请号：PCT/US1995016880

申请日：1995-12-28

Applicant: INTEL CORPORATION

Inventor： INTEL CORPORATION ,  HAYEK, George, R. ,  NARDONE, Joe, M. ,  KUNDU, Aniruddha ,  BAINS, Kuljit, S.

IPC: G11C07/00

CPC classification number: G11C7/1018 ,  G11C7/1024

Abstract: A memory controller (105) having a data strobe (250) that tracks the column address strobe signal in a computer system having Extended Data Out (EDO) DRAMs (230). The data strobe signal follows, by a predetermined delay, the column access strobe signal, and therefore any skew in the column address strobe signal is inherently included within the data strobe signal. As a result, the data can be latched out, responsive to the data strobe signal, at approximately the center of the valid window.

Abstract translation: 具有在具有扩展数据输出（EDO）DRAM（230）的计算机系统中跟踪列地址选通信号的数据选通（250）的存储器控​​制器（105）。 数据选通信号以预定的延迟跟随列存取选通信号，因此列地址选通信号中的任何偏移固有地包括在数据选通信号内。 结果，可以在有效窗口的大约中心处响应于数据选通信号来锁存数据。

公开(公告)号：WO1996019770A1

公开(公告)日：1996-06-27

申请号：PCT/US1995016606

申请日：1995-12-19

Applicant: INTEL CORPORATION

Inventor： INTEL CORPORATION ,  CHITTOR, Suresh, S.

IPC: G06F11/34

CPC classification number: H04L49/557 ,  H04L49/1576 ,  H04L49/555

Abstract: A method and apparatus for enhancing the fault-tolerance of a network finds a set of computing nodes within the network which are available for use in the network upon detection of a faulty component. This set of available computing nodes is found by first determining a set of computing nodes within the network which are physically connected together. A connectivity value for each computing node within this set is then determined. A subset of the set is then generated such that each computing node in the subset is able to transfer data to and from each other computing node in the subset. This subset is then utilized as the set of available computing nodes. In one embodiment, the set of computing nodes which are physically connected together is the largest set of physically connected computing nodes in the system.

Abstract translation: 一种用于增强网络的容错能力的方法和设备找到网络中的一组可用于在检测到故障组件时在网络中使用的计算节点。 通过首先确定网络中物理连接在一起的一组计算节点来找到该组可用的计算节点。 然后确定该组内每个计算节点的连接值。 然后生成集合的子集，使得子集中的每个计算节点能够向子集中的每个其他计算节点传送数据。 然后将该子集用作可用计算节点的集合。 在一个实施例中，物理连接在一起的计算节点的集合是系统中最大的物理连接的计算节点集合。

公开(公告)号：WO1996019764A1

公开(公告)日：1996-06-27

申请号：PCT/US1995016337

申请日：1995-12-14

Applicant: INTEL CORPORATION

Inventor： INTEL CORPORATION ,  DUNSTAN, Robert, A. ,  SILVESTER, Kelan

IPC: G06F01/00

CPC classification number: G06F1/3215 ,  G06F1/26

Abstract: A computer system (10) that provides device specific power characterizations for power control and budgeting functions is disclosed. The device driver programs of the computer system (10) or a power characterizer of the system (50) determines device specific power characterizations for corresponding devices (94, 96, 98) under device specific controlled conditions. The device specific power characterizations are stored in persistent storage for subsequent use by power control and budgeting functions.

Abstract translation: 公开了一种为功率控制和预算功能提供设备特定功率特性的计算机系统（10）。 计算机系统（10）的设备驱动程序或系统（50）的功率表征器在设备特定控制条件下确定相应设备（94,96,98）的设备特定功率特性。 设备特定的功率特征存储在持久存储器中，以便后续使用功率控制和预算功能。

公开(公告)号：WO1996013768A1

公开(公告)日：1996-05-09

申请号：PCT/US1995013884

申请日：1995-10-26

Applicant: INTEL CORPORATION

Inventor： INTEL CORPORATION ,  PIERCE, Michael, E. ,  SCHEER, David, C.

IPC: G06F01/32

CPC classification number: G06F1/3215 ,  G05F1/575 ,  G06F1/325

Abstract: A system for controlling the power consumption of an add-in PC card (10) operating within a host computer. The host computer includes a power supply (24) that provides all power used by the PC card (10). The PC card includes communication registers required for communication between the host computer and the PC card. The PC card also includes a microcontroller (26) connected to an I/O subsystem (32) and a multi-pin I/O connector (36). A first side of multi-pin I/O connector (36) is connected to the I/O subsystem and second side (38) is connected to a source of I/O signals external to the host computer. An external register module (16) is connected to the microcontroller (26) and communicates with the host computer. The external register module (16) contains the communication registers. A status detector located on the PC card (10) detects whether the I/O subsystem (32) is processing I/O information, and supplies a status signal indicative thereof. A power management module (68) is also located on the PC card (10) and is connected to the status connector. The power management module receives the status signal from the status detector and supplies one or more predetermined power levels as a result of the status signal.

Abstract translation: 一种用于控制在主计算机内操作的附加PC卡（10）的功耗的系统。 主计算机包括提供PC卡（10）使用的所有电力的电源（24）。 PC卡包括主计算机和PC卡之间通信所需的通信寄存器。 PC卡还包括连接到I / O子系统（32）和多针I / O连接器（36）的微控制器（26）。 多引脚I / O连接器（36）的第一侧连接到I / O子系统，第二侧（38）连接到主计算机外部的I / O信号源。 外部寄存器模块（16）连接到微控制器（26）并与主机通信。 外部寄存器模块（16）包含通信寄存器。 位于PC卡（10）上的状态检测器检测I / O子系统（32）是否正在处理I / O信息，并提供指示其的状态信号。 电源管理模块（68）也位于PC卡（10）上，并连接到状态连接器。 电源管理模块从状态检测器接收状态信号，并作为状态信号的结果提供一个或多个预定功率电平。

公开(公告)号：WO1996012295A1

公开(公告)日：1996-04-25

申请号：PCT/US1995009529

申请日：1995-07-14

Applicant: INTEL CORPORATION

Inventor： INTEL CORPORATION ,  MYERS, Alan, M. ,  CHARVAT, Peter, K. ,  LETSON, Thomas, A. ,  YANG, Shi-ning ,  BAI, Peng

IPC: H01L21/302

CPC classification number: H01L21/76805 ,  H01L21/32133 ,  H01L21/32134 ,  H01L21/76838 ,  H01L23/5226 ,  H01L23/53223 ,  H01L2924/0002 ,  H01L2924/3011 ,  Y10S257/915 ,  H01L2924/00

Abstract: A novel high performance and reliable interconnection structure for preventing via delamination. The interconnection structure of the present invention comprises a via connection (212) which extends into and undercuts an underlying interconnection line (202) to lock the via connection (212) into the interconnection line (202).

Abstract translation: 一种新颖的高性能和可靠的互连结构，用于防止通过分层。 本发明的互连结构包括一个通孔连接（212），该通孔连接（212）延伸到下面的互连线（202）并将其下切以将通孔连接（212）锁定到互连线（202）中。

公开(公告)号：WO1996010888A1

公开(公告)日：1996-04-11

申请号：PCT/US1995010662

申请日：1995-08-22

Applicant: INTEL CORPORATION

Inventor： INTEL CORPORATION ,  ADAMS, Robert ,  WILLIAMS, David, M. ,  RICHARDSON, John ,  PERRY, Burt

IPC: H04N05/50

CPC classification number: H04L65/4076 ,  G06F3/14 ,  H04L29/06 ,  H04L29/06027 ,  H04L65/604 ,  H04N5/04 ,  H04N5/44 ,  H04N5/4401 ,  H04N5/44513 ,  H04N5/44591 ,  H04N7/088 ,  H04N21/4143 ,  H04N21/42676 ,  H04N21/4307 ,  H04N21/4312 ,  H04N21/4316 ,  H04N21/4348 ,  H04N21/435 ,  H04N21/4438 ,  H04N21/4622 ,  H04N21/482

Abstract: An interactive video system is disclosed that processes a video data stream and an associated data stream corresponding to the video data stream. The interactive video system displays a video image defined by the video data stream on a display device (50) and performs interactive command functions specified by the associated data stream. The interactive command functions include commands that specify placement of a video display window (40), commands that specify parameters of graphical objects (44) that are associated with the video image and commands that specify pixel data or graphics description for the graphical object and commands for placement of selection windows (42) and that specify interactive functions for the selection windows.

Abstract translation: 公开了一种交互式视频系统，其处理与视频数据流相对应的视频数据流和相关联的数据流。 交互式视频系统在显示设备（50）上显示由视频数据流定义的视频图像，并且执行由相关联的数据流指定的交互式命令功能。 交互式命令功能包括指定视频显示窗口（40）的放置的命令，指定与视频图像相关联的图形对象（44）的参数的命令以及为图形对象和命令指定像素数据或图形描述的命令 用于放置选择窗口（42），并为选择窗口指定交互式功能。

公开(公告)号：WO1996008092A1

公开(公告)日：1996-03-14

申请号：PCT/US1995011136

申请日：1995-09-01

Applicant: INTEL CORPORATION

Inventor： INTEL CORPORATION ,  DAVIS, Derek, L.

IPC: H04K01/00

CPC classification number: G07F7/1008 ,  G06F12/1408 ,  G06F21/00 ,  G06F21/10 ,  G06F21/445 ,  G06F21/72 ,  G06F2211/007 ,  G06F2221/0797 ,  G06F2221/2103 ,  G06F2221/2153 ,  G06Q20/341 ,  G06Q20/3552 ,  G06Q20/40975 ,  H04L63/0823 ,  H04L63/10 ,  H04L2463/101

Abstract: An integrated circuit component for enforcing licensing restrictions. Such enforcement is performed through remote transmission of access privileges for executing a licensed program from the integrated circuit component to another similar component. The integrated circuit component comprising a non-volatile memory for storing a uniquely designated key pair (11, 12), an authentication device certificate (80) and a manufacturer public key (16) along with cryptographic algorithms, a processor for executing the cryptographic algorithms in order to process information inputted into the integrated circuit component and for transmitting the processed information into volatile memory and a random number generator for generating the uniquely designated key pair internally within the integrated circuit component.

Abstract translation: 用于执行许可限制的集成电路组件。 这种执行是通过将执行许可程序的访问权限从集成电路组件远程传送到另一个类似的组件来执行的。 所述集成电路部件包括用于存储唯一指定的密钥对（11,12）的非易失性存储器，认证设备证书（80）和制造商公开密钥（16）以及加密算法，用于执行密码算法 以便处理输入到集成电路部件中的信息并将处理的信息发送到易失性存储器中，以及随机数发生器，用于在集成电路部件内部产生唯一指定的密钥对。

公开(公告)号：WO1996006390A2

公开(公告)日：1996-02-29

申请号：PCT/US1995009896

申请日：1995-08-04

Applicant: INTEL CORPORATION

Inventor： INTEL CORPORATION ,  WANG, Wen-Hann ,  LAI, Konrad, K.

IPC: G06F00/00

CPC classification number: G06F12/0864

Abstract: A two-way set-associative cache memory includes both a set array and a data array in one embodiment. The data array comprises multiple elements, each of which can contain a cache line. The set array comprises multiple sets, with each set in the set array corresponding to an element in the data array. Each set in the set array contains information which indicates whether an address received by the cache memory matches the cache line contained in its corresponding element of the data array. The information stored in each set includes a tag and a state. The tag contains a reference to one of the cache lines in the data array. If the tag of a particular set matches the address received by the cache memory, then the cache line associated with that particular set is the requested cache line. The state of a particular set indicates the number of cache lines mapped into that particular set.

Abstract translation: 双向组相关高速缓冲存储器在一个实施例中包括集阵列和数据阵列。 数据阵列包括多个元素，每个元素可以包含高速缓存行。 集合阵列包括多个集合，集合阵列中的每个集合对应于数据数组中的一个元素。 集合阵列中的每个集合包含指示高速缓冲存储器接收的地址与数据阵列的相应元素中包含的高速缓存行匹配的信息。 存储在每个集合中的信息包括标签和状态。 标签包含对数据数组中的一条缓存行的引用。 如果特定集合的标签与高速缓存存储器接收的地址匹配，则与该特定集合相关联的高速缓存行是所请求的高速缓存行。 特定集合的状态指示映射到该特定集合的高速缓存行数。