公开(公告)号：US20230073078A1

公开(公告)日：2023-03-09

申请号：US17445856

申请日：2021-08-25

Applicant: Intel Corporation

Inventor： Willy Rachmady ,  Sudipto Naskar ,  Cheng-Ying Huang ,  Gilbert Dewey ,  Marko Radosavljevic ,  Nicole K. Thomas ,  Patrick Morrow ,  Urusa Alaan

IPC: H01L27/12

Abstract: An integrated circuit structure having a stacked transistor architecture includes a first semiconductor body (e.g., set of one or more nanoribbons) and a second semiconductor body (e.g., set of one or more nanoribbons) above the first semiconductor body. The first and second semiconductor bodies are part of the same fin structure. The distance between an upper surface of the first semiconductor body and a lower surface of the second semiconductor body is 60 nm or less. A first gate structure is on the first semiconductor body, and a second gate structure is on the second semiconductor body. An isolation structure that includes a dielectric material is between the first and second gate structures, and is on and conformal to a top surface of the first gate structure. In addition, a bottom surface of the second gate structure is on a top surface of the isolation structure, which is relatively flat.

公开(公告)号：US11594533B2

公开(公告)日：2023-02-28

申请号：US16455667

申请日：2019-06-27

Applicant: Intel Corporation

Inventor： Willy Rachmady ,  Cheng-Ying Huang ,  Gilbert Dewey ,  Aaron Lilak ,  Patrick Morrow ,  Anh Phan ,  Ehren Mannebach ,  Jack T. Kavalieros

IPC: H01L21/8238 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/66

Abstract: A device is disclosed. The device includes a first semiconductor fin, a first source-drain epitaxial region adjacent a first portion of the first semiconductor fin, a second source-drain epitaxial region adjacent a second portion of the first semiconductor fin, a first gate conductor above the first semiconductor fin, a gate spacer covering the sides of the gate conductor, a second semiconductor fin below the first semiconductor fin, a second gate conductor on a first side of the second semiconductor fin and a third gate conductor on a second side of the second semiconductor fin, a third source-drain epitaxial region adjacent a first portion of the second semiconductor fin, and a fourth source-drain epitaxial region adjacent a second portion of the second semiconductor fin. The device also includes a dielectric isolation structure below the first semiconductor fin and above the second semiconductor fin that separates the first semiconductor fin and the second semiconductor fin.

公开(公告)号：US11563119B2

公开(公告)日：2023-01-24

申请号：US16650834

申请日：2017-12-27

Applicant: Intel Corporation

Inventor： Cheng-Ying Huang ,  Willy Rachmady ,  Gilbert Dewey ,  Erica J. Thompson ,  Aaron D. Lilak ,  Jack T. Kavalieros

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/165

Abstract: Disclosed are etchstop regions in fins of semiconductor devices, and related methods. A semiconductor device includes a buried region, a fin on the buried region, and a gate formed at least partially around the fin. At least a portion of the fin that borders the buried region includes an etchstop material. The etchstop material includes a doped semiconductor material that has a slower etch rate than that of an intrinsic form of the semiconductor material. A method of manufacturing a semiconductor device includes forming a gate on a fin, implanting part of the fin with dopants configured to decrease an etch rate of the part of the fin, removing at least part of the fin, and forming an epitaxial semiconductor material on a remaining proximal portion of the fin.

公开(公告)号：US11532619B2

公开(公告)日：2022-12-20

申请号：US16367175

申请日：2019-03-27

Applicant: Intel Corporation

Inventor： Willy Rachmady ,  Cheng-Ying Huang ,  Gilbert Dewey ,  Jack Kavalieros ,  Caleb Barrett ,  Jay P. Gupta ,  Nishant Gupta ,  Kaiwen Hsu ,  Byungki Jung ,  Aravind S. Killampalli ,  Justin Railsback ,  Supanee Sukrittanon ,  Prashant Wadhwa

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/16 ,  H01L29/78 ,  H01L21/02 ,  H01L21/8234 ,  H01L29/423

Abstract: Transistor structures including a non-planar body that has an active portion comprising a semiconductor material of a first height that is variable, and an inactive portion comprising an oxide of the semiconductor material of a second variable height, complementary to the first height. Gate electrodes and source/drain terminals may be coupled through a transistor channel having any width that varies according to the first height. Oxidation of a semiconductor material may be selectively catalyzed to convert a desired portion of a non-planar body into the oxide of the semiconductor material. Oxidation may be enhanced through the application of a catalyst, such as one comprising metal and oxygen, for example.

公开(公告)号：US20220278227A1

公开(公告)日：2022-09-01

申请号：US17745822

申请日：2022-05-16

Applicant: Intel Corporation

Inventor： Cheng-Ying Huang ,  Jack Kavalieros ,  Ian Young ,  Matthew Metz ,  Willy Rachmady ,  Uygar Avci ,  Ashish Agrawal ,  Benjamin Chu-Kung

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/417 ,  H01L29/786

Abstract: Tunneling Field Effect Transistors (TFETs) are promising devices in that they promise significant performance increase and energy consumption decrease due to a steeper subthreshold slope (for example, smaller sub-threshold swing). In various embodiments, vertical fin-based TFETs can be fabricated in trenches, for example, silicon trenches. In another embodiment, vertical TFETs can be used on different material systems acting as a substrate and/or trenches (for example, Si, Ge, III-V semiconductors, GaN, and the like). In one embodiment, the tunneling direction in the channel of the vertical TFET can be perpendicular to the Si substrates. In one embodiment, this can be different than the tunneling direction in the channel of lateral TFETs.

公开(公告)号：US20220223519A1

公开(公告)日：2022-07-14

申请号：US17709032

申请日：2022-03-30

Applicant: Intel Corporation

Inventor： Gilbert Dewey ,  Ryan Keech ,  Cory Bomberger ,  Cheng-Ying Huang ,  Ashish Agrawal ,  Willy Rachmady ,  Anand Murthy

IPC: H01L23/522 ,  H01L21/768 ,  H01L21/762 ,  H01L27/12

Abstract: A device includes a device level having a metallization structure coupled to a semiconductor device and a transistor above the device level. The transistor has a body including a single crystal group III-V or group IV semiconductor material, a source structure on a first portion of the body and a drain structure on a second portion of the body, where the source structure is separate from the drain structure. The transistor further includes a gate structure including a first gate structure portion in a recess in the body and a second gate structure portion between the source structure and the drain structure. A source contact is coupled with the source structure and a drain contact is coupled with the drain structure. The source contact is in contact with the metallization structure in the device level.

公开(公告)号：US11355621B2

公开(公告)日：2022-06-07

申请号：US16648199

申请日：2018-01-12

Applicant: Intel Corporation

Inventor： Gilbert Dewey ,  Willy Rachmady ,  Sean Ma ,  Nicholas Minutillo ,  Tahir Ghani ,  Matthew V. Metz ,  Cheng-Ying Huang ,  Anand S. Murthy

IPC: H01L21/02 ,  H01L29/16 ,  H01L29/66 ,  H01L29/205 ,  H01L29/78

Abstract: Techniques and mechanisms for providing functionality of a non-planar device which includes a semiconductor body disposed on a dielectric layer and over an underlying subfin region. In an embodiment, the dielectric layer is disposed between, and adjoins each of, a first semiconductor material of the subfin region and a second semiconductor material of semiconductor body. The dielectric layer is an artefact of fabrication processing wherein an epitaxy of the semiconductor body is grown horizontally along a length of the subfin region. During such epitaxial growth, the dielectric layer prevents vertical growth of the second semiconductor material from the subfin region. Moreover, at least a portion of a dummy gate determines a shape of the semiconductor body. In another embodiment, formation of the semiconductor body is preceded by an etching to remove a section of a fin portion which is disposed over the subfin region.

公开(公告)号：US11335796B2

公开(公告)日：2022-05-17

申请号：US16645758

申请日：2017-12-30

Applicant: Intel Corporation

Inventor： Cheng-Ying Huang ,  Willy Rachmady ,  Matthew V. Metz ,  Gilbert Dewey ,  Sean T. Ma ,  Jack T. Kavalieros

IPC: H01L29/778 ,  H01L21/02 ,  H01L29/08 ,  H01L29/15 ,  H01L29/205 ,  H01L29/66

Abstract: Embodiments herein describe techniques, systems, and method for a semiconductor device. Embodiments herein may present a semiconductor device including a substrate, and a channel area above the substrate and including a first III-V material. A source area may be above the substrate and including a second III-V material. An interface between the channel area and the source area may include the first III-V material. The source area may include a barrier layer of a third III-V material above the substrate. A current is to flow between the source area and the channel area through the barrier layer. Other embodiments may be described and/or claimed.

公开(公告)号：US11177255B2

公开(公告)日：2021-11-16

申请号：US16650823

申请日：2018-01-05

Applicant: Intel Corporation

Inventor： Sean T. Ma ,  Willy Rachmady ,  Gilbert Dewey ,  Matthew V. Metz ,  Harold W. Kennel ,  Cheng-Ying Huang ,  Jack T. Kavalieros ,  Anand S. Murthy ,  Tahir Ghani

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786 ,  H01L21/02 ,  H01L21/28 ,  H01L29/66 ,  H01L21/8252

Abstract: Embodiments include a first nanowire transistor having a first source and a first drain with a first channel in between, where the first channel includes a first III-V alloy. A first gate stack is around the first channel, where a portion of the first gate stack is between the first channel and a substrate. The first gate stack includes a gate electrode metal in contact with a gate dielectric. A second nanowire transistor is on the substrate, having a second source and a second drain with a second channel therebetween, the second channel including a second III-V alloy. A second gate stack is around the second channel, where an intervening material is between the second gate stack and the substrate, the intervening material including a third III-V alloy. The second gate stack includes the gate electrode metal in contact with the gate dielectric.

公开(公告)号：US20210074828A1

公开(公告)日：2021-03-11

申请号：US16649183

申请日：2017-12-26

Applicant: Intel Corporation

Inventor： Willy Rachmady ,  Cheng-Ying Huang ,  Gilbert Dewey

IPC: H01L29/51 ,  H01L23/367 ,  H01L23/16 ,  H01L23/00 ,  H01L27/092 ,  H01L29/08 ,  H01L29/45 ,  H01L29/78 ,  H01L21/285 ,  H01L29/66

Abstract: An embodiment includes a system comprising: a switching device that includes a fin; and a source contact on a source, a gate contact on a channel, and a drain contact on a drain; wherein the gate contact includes: (a)(i) a first layer that includes oxygen, the first layer directly contacting the fin, (a)(ii) a second layer that includes a dielectric material, (c) a third layer that includes at least one of aluminum, titanium, ruthenium, zirconium, hafnium, tantalum, niobium, vanadium, thorium, barium, magnesium, cerium, and lanthanum, and (a)(iii) a fourth layer that includes a metal, wherein (b)(i) the source contact, the gate contact, and the drain contact are all on the fin, and (b)(ii) the second layer is between the first and fourth layers. Other embodiments are described herein.