公开(公告)号：US20150060908A1

公开(公告)日：2015-03-05

申请号：US14475638

申请日：2014-09-03

Applicant: Sensor Electronic Technology, Inc.

Inventor： Rakesh Jain ,  Maxim S. Shatalov ,  Jinwei Yang ,  Alexander Dobrinsky ,  Michael Shur ,  Remigijus Gaska

IPC: H01L33/14 ,  H01S5/323 ,  H01L31/0352 ,  H01L33/32 ,  H01L31/0304

CPC classification number: H01L31/035272 ,  H01L33/04 ,  H01L33/32

Abstract: An improved heterostructure for an optoelectronic device is provided. The heterostructure includes an active region, an electron blocking layer, and a p-type contact layer. The p-type contact layer and electron blocking layer can be doped with a p-type dopant. The dopant concentration for the electron blocking layer can be at most ten percent the dopant concentration of the p-type contact layer. A method of designing such a heterostructure is also described.

Abstract translation: 提供了一种用于光电子器件的改进的异质结构。 异质结构包括有源区，电子阻挡层和p型接触层。 p型接触层和电子阻挡层可以掺杂有p型掺杂剂。 电子阻挡层的掺杂剂浓度可以是p型接触层的掺杂剂浓度的至多10％。 还描述了设计这种异质结构的方法。

公开(公告)号：US20140191398A1

公开(公告)日：2014-07-10

申请号：US14150949

申请日：2014-01-09

Applicant: Sensor Electronic Technology, Inc.

Inventor： Remigijus Gaska ,  Maxim S. Shatalov ,  Alexander Lunev ,  Alexander Dobrinsky ,  Jinwei Yang ,  Michael Shur

IPC: H01L33/22 ,  H01L33/00 ,  H01L33/36

CPC classification number: H01L33/22 ,  H01L24/05 ,  H01L24/14 ,  H01L33/32 ,  H01L33/38 ,  H01L2224/0401 ,  H01L2224/06102 ,  H01L2224/1134 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2933/0016 ,  H01L2924/00

Abstract: A device including a first semiconductor layer and a contact to the first semiconductor layer is disclosed. An interface between the first semiconductor layer and the contact includes a first roughness profile having a characteristic height and a characteristic width. The characteristic height can correspond to an average vertical distance between crests and adjacent valleys in the first roughness profile. The characteristic width can correspond to an average lateral distance between the crests and adjacent valleys in the first roughness profile.

Abstract translation: 公开了一种包括第一半导体层和与第一半导体层的接触的器件。 第一半导体层和触点之间的界面包括具有特征高度和特征宽度的第一粗糙度轮廓。 特征高度可以对应于第一粗糙度轮廓中波峰和相邻谷之间的平均垂直距离。 特征宽度可以对应于第一粗糙度轮廓中的波峰和相邻谷之间的平均横向距离。

公开(公告)号：US20140134773A1

公开(公告)日：2014-05-15

申请号：US13647902

申请日：2012-10-09

Applicant: Sensor Electronic Technology, Inc.

Inventor： Rakesh Jain ,  Wenhong Sun ,  Jinwei Yang ,  Maxim S. Shatalov ,  Alexander Dobrinsky ,  Michael Shur ,  Remigijus Gaska

IPC: H01L33/12

CPC classification number: H01L33/22 ,  H01L21/0242 ,  H01L21/0243 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/02639 ,  H01L21/0265 ,  H01L21/02658 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/34 ,  H01L29/66462 ,  H01L29/778 ,  H01L29/7787 ,  H01L33/007 ,  H01L33/06 ,  H01L33/10 ,  H01L33/12 ,  H01L33/24 ,  H01L33/32 ,  H01L2933/0091

Abstract: A method of fabricating a device using a layer with a patterned surface for improving the growth of semiconductor layers, such as group III nitride-based semiconductor layers with a high concentration of aluminum, is provided. The patterned surface can include a substantially flat top surface and a plurality of stress reducing regions, such as openings. The substantially flat top surface can have a root mean square roughness less than approximately 0.5 nanometers, and the stress reducing regions can have a characteristic size between approximately 0.1 microns and approximately five microns and a depth of at least 0.2 microns. A layer of group-III nitride material can be grown on the first layer and have a thickness at least twice the characteristic size of the stress reducing regions.

Abstract translation: 提供了使用具有图案化表面的层以改善半导体层生长的器件的方法，例如具有高浓度铝的III族氮化物基半导体层。 图案化表面可以包括基本上平坦的顶表面和多个减压区域，例如开口。 基本上平坦的顶表面可以具有小于约0.5纳米的均方根粗糙度，并且应力减小区域可以具有在约0.1微米至约5微米之间的特征尺寸和至少0.2微米的深度。 III族氮化物材料层可以在第一层上生长并且具有至少是应力减小区域的特征尺寸的两倍的厚度。

公开(公告)号：US20130221406A1

公开(公告)日：2013-08-29

申请号：US13775038

申请日：2013-02-22

Applicant: Sensor Electronic Technology, Inc.

Inventor： Remigijus Gaska ,  Michael Shur ,  Jinwei Yang ,  Alexander Dobrinsky ,  Maxim S. Shatalov

IPC: H01L29/66 ,  H01L29/778

CPC classification number: H01L29/452 ,  H01L21/28575 ,  H01L29/155 ,  H01L29/2003 ,  H01L29/201 ,  H01L29/205 ,  H01L29/401 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/737 ,  H01L29/778 ,  H01L29/7786 ,  H01L33/007 ,  H01L33/0075 ,  H01L33/06 ,  H01L33/14 ,  H01L33/32 ,  H01L33/40 ,  H01L33/405 ,  H01L2933/0016

Abstract: A solution for forming an ohmic contact to a semiconductor layer is provided. A masking material is applied to a set of contact regions on the surface of the semiconductor layer. Subsequently, one or more layers of a device heterostructure are formed on the non-masked region(s) of the semiconductor layer. The ohmic contact can be formed after the one or more layers of the device heterostructure are formed. The ohmic contact formation can be performed at a processing temperature lower than a temperature range within which a quality of a material forming any semiconductor layer in the device heterostructure is damaged.

Abstract translation: 提供了用于形成与半导体层的欧姆接触的解决方案。 掩模材料被施加到半导体层表面上的一组接触区域。 随后，在半导体层的非掩蔽区域上形成一层或多层器件异质结构。 欧姆接触可以在形成器件异质结构的一个或多个层之后形成。 欧姆接触形成可以在低于在器件异质结构中形成任何半导体层的材料的质量被损坏的温度范围的处理温度下进行。