公开(公告)号：US20170309722A1

公开(公告)日：2017-10-26

申请号：US15644850

申请日：2017-07-10

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Fang Tzou ,  Chien-Ming Lai ,  Yi-Wen Chen ,  Hung-Yi Wu ,  Tong-Jyun Huang ,  Chien-Ting Lin ,  Chun-Hsien Lin

IPC: H01L29/49 ,  H01L29/423 ,  H01L21/8238 ,  H01L29/66

CPC classification number: H01L29/4966 ,  H01L21/823842 ,  H01L21/823864 ,  H01L29/42364 ,  H01L29/66545

Abstract: A metal gate transistor includes a substrate, a metal gate on the substrate, and a source/drain region in the substrate adjacent to the metal gate. The metal gate includes a high-k dielectric layer, a bottom barrier metal (BBM) layer comprising TiSiN on the high-k dielectric layer, a TiN layer on the BBM layer, a TiAl layer between the BBM layer and the TiN layer, and a low resistance metal layer on the TiN layer.

公开(公告)号：US09711411B2

公开(公告)日：2017-07-18

申请号：US14963216

申请日：2015-12-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Lin Lu ,  Shih-Fang Tzou ,  Chun-Lung Chen ,  Kun-Yuan Liao ,  Feng-Yi Chang ,  Wei-Hao Huang

IPC: H01L21/8234 ,  H01L27/092 ,  H01L21/02 ,  H01L21/311 ,  H01L21/768

CPC classification number: H01L21/823431 ,  H01L21/02164 ,  H01L21/02167 ,  H01L21/31116 ,  H01L21/76897 ,  H01L21/823468 ,  H01L21/823475 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/0924

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a first gate structure and a second gate structure on the substrate; forming a contact etch stop layer (CESL) on the first gate structure, the second gate structure, and the substrate; removing part of the CESL between the first gate structure and the second gate structure; and forming an interlayer dielectric (ILD) layer on the CESL.

公开(公告)号：US09443952B2

公开(公告)日：2016-09-13

申请号：US14506009

申请日：2014-10-03

Applicant: United Microelectronics Corp.

Inventor： Chun-Tsen Lu ,  Chih-Jung Su ,  Jian-Wei Chen ,  Shui-Yen Lu ,  Yi-Wen Chen ,  Po-Cheng Huang ,  Chen-Ming Huang ,  Shih-Fang Tzou

IPC: H01L21/3205 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/49 ,  H01L29/51

CPC classification number: H01L29/66545 ,  H01L21/0206 ,  H01L21/02065 ,  H01L21/02271 ,  H01L21/31053 ,  H01L21/31055 ,  H01L21/311 ,  H01L21/31144 ,  H01L21/823431 ,  H01L21/823821 ,  H01L29/4966 ,  H01L29/517

Abstract: A method of forming a semiconductor device is disclosed. A substrate having multiple fins is provided. An insulating layer fills a lower portion of a gap between two adjacent fins. At least one first stacked structure is formed on one fin and at least one second stacked structure is formed on one insulation layer. A first dielectric layer is formed to cover the first and second stacked structures. A portion of the first dielectric layer and portions of the first and second stacked structures are removed. Another portion of the first dielectric layer is removed until a top of the remaining first dielectric layer is lower than tops of the first and second stacked structures. A second dielectric layer is formed to cover the first and second stacked structures. A portion of the second dielectric layer is removed until the tops of the first and second stacked structures are exposed.

Abstract translation: 公开了一种形成半导体器件的方法。 提供具有多个翅片的基板。 绝缘层填充两个相邻翅片之间的间隙的下部。 在一个翅片上形成至少一个第一堆叠结构，并且在一个绝缘层上形成至少一个第二堆叠结构。 形成第一电介质层以覆盖第一和第二堆叠结构。 去除第一电介质层的一部分和第一和第二堆叠结构的部分。 去除第一电介质层的另一部分，直到剩余的第一电介质层的顶部低于第一和第二堆叠结构的顶部。 形成第二电介质层以覆盖第一和第二堆叠结构。 去除第二电介质层的一部分直到第一和第二堆叠结构的顶部露出。

公开(公告)号：US20160104645A1

公开(公告)日：2016-04-14

申请号：US14536696

申请日：2014-11-10

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Wen Hung ,  Chih-Sen Huang ,  Yi-Wei Chen ,  Chien-Ting Lin ,  Shih-Fang Tzou ,  Chia-Lin Lu ,  Chun-Lung Chen ,  Kun-Yuan Liao ,  Feng-Yi Chang ,  Chieh-Te Chen

IPC: H01L21/8234 ,  H01L21/311 ,  H01L29/49 ,  H01L29/06 ,  H01L27/088 ,  H01L21/02 ,  H01L21/768

CPC classification number: H01L21/823437 ,  H01L21/31144 ,  H01L21/76816 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823431 ,  H01L21/823475 ,  H01L27/088 ,  H01L27/0886 ,  H01L29/0653 ,  H01L29/495 ,  H01L29/4966

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a plurality of gate structures on the substrate; forming a first stop layer on the gate structures; forming a second stop layer on the first stop layer; forming a first dielectric layer on the second stop layer; forming a plurality of first openings in the first dielectric layer to expose the second stop layer; forming a plurality of second openings in the first dielectric layer and the second stop layer to expose the first stop layer; and removing part of the second stop layer and part of the first stop layer to expose the gate structures.

Abstract translation: 公开了半导体器件的制造方法。 该方法包括以下步骤：提供衬底; 在所述基板上形成多个栅极结构; 在栅极结构上形成第一阻挡层; 在所述第一停止层上形成第二停止层; 在所述第二停止层上形成第一电介质层; 在所述第一电介质层中形成多个第一开口以露出所述第二阻挡层; 在所述第一介电层和所述第二停止层中形成多个第二开口以暴露所述第一停止层; 以及去除所述第二停止层的一部分和所述第一停止层的一部分以暴露所述栅极结构。

公开(公告)号：US09281199B2

公开(公告)日：2016-03-08

申请号：US14639134

申请日：2015-03-05

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Wen Hung ,  Chih-Sen Huang ,  Po-Chao Tsao ,  Shih-Fang Tzou

IPC: H01L29/76 ,  H01L21/28 ,  H01L29/78 ,  H01L29/66 ,  H01L21/311 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/485

CPC classification number: H01L21/28079 ,  H01L21/28008 ,  H01L21/28088 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/32053 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76897 ,  H01L23/485 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for fabricating a semiconductor device includes the following steps. First, a first interlayer dielectric is formed on a substrate. Then, a gate electrode is formed on the substrate so that the periphery of the gate electrode is surrounded by the first interlayer dielectric. Afterwards, a patterned mask layer is formed on the gate electrode, and a bottom surface of the patterned mask layer is level with a top surface of the first interlayer dielectric. A spacer is then formed on each sidewall of the gate electrode. Subsequently, a second interlayer dielectric is formed to cover a top surface and each side surface of the patterned mask layer. Finally, a self-aligned contact structure is formed in the first interlayer dielectric and the second interlayer dielectric.

Abstract translation: 一种制造半导体器件的方法包括以下步骤。 首先，在基板上形成第一层间电介质。 然后，在基板上形成栅电极，使得栅电极的周围被第一层间电介质包围。 之后，在栅电极上形成图案化掩模层，并且图案化掩模层的底表面与第一层间电介质的顶表面平齐。 然后在栅电极的每个侧壁上形成间隔物。 随后，形成第二层间电介质以覆盖图案化掩模层的顶表面和每个侧表面。 最后，在第一层间电介质和第二层间电介质中形成自对准接触结构。

公开(公告)号：US20150380506A1

公开(公告)日：2015-12-31

申请号：US14844504

申请日：2015-09-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Jun-Jie Wang ,  Po-Chao Tsao ,  Chia-Jui Liang ,  Shih-Fang Tzou ,  Chien-Ting Lin ,  Cheng-Guo Chen ,  Ssu-I Fu ,  Yu-Hsiang Hung ,  Chung-Fu Chang

IPC: H01L29/423 ,  H01L29/51 ,  H01L29/78

CPC classification number: H01L29/42364 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/513 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/7851

Abstract: A replacement gate process is disclosed. A substrate and a dummy gate structure formed on the substrate is provided, wherein the dummy gate structure comprises a dummy layer on the substrate, a hard mask layer on the dummy layer, spacers at two sides of the dummy layer and the hard mask layer, and a contact etch stop layer (CESL) covering the substrate, the spacers and the hard mask layer. The spacers and the CESL are made of the same material. Then, a top portion of the CESL is removed to expose the hard mask layer. Next, the hard mask layer is removed. Afterward, the dummy layer is removed to form a trench.

Abstract translation: 公开了替代浇口工艺。 提供了一种在基板上形成的基板和虚拟栅极结构，其中，虚设栅极结构包括基板上的虚设层，虚设层上的硬掩模层，虚设层两侧的间隔物和硬掩模层， 以及覆盖衬底，间隔物和硬掩模层的接触蚀刻停止层（CESL）。 垫片和CESL由相同的材料制成。 然后，去除CESL的顶部以露出硬掩模层。 接下来，去除硬掩模层。 之后，去除虚拟层以形成沟槽。

公开(公告)号：US20150347657A1

公开(公告)日：2015-12-03

申请号：US14822907

申请日：2015-08-11

Applicant: United Microelectronics Corp.

Inventor： Po-Chao Tsao ,  Shih-Fang Hong ,  Chia-Wei Huang ,  Ming-Jui Chen ,  Shih-Fang Tzou ,  Ming-Te Wei

IPC: G06F17/50 ,  G03F1/36

CPC classification number: G06F17/5068 ,  G03F1/144 ,  G03F1/36

Abstract: A method of generating a layout pattern including a FinFET structure layout includes the following processes. First, a layout pattern, which includes a sub-pattern having pitches in simple integer ratios, is provided to a computer system. The sub-pattern is then classified into a first sub-pattern and a second sub-pattern. Afterwards, first stripe patterns and at least one second stripe pattern are generated. The longitudinal edges of the first stripe patterns are aligned with the longitudinal edges of the first sub-pattern and the first stripe patterns have equal spacings and widths. The positions of the second stripe patterns correspond to the positions of the blank pattern, and spacings or widths of the second stripe patterns are different from the spacings or widths of the first stripe patterns. Finally, the first stripe patterns and the second stripe pattern are outputted to a photomask.

Abstract translation: 生成包括FinFET结构布局的布局图案的方法包括以下处理。 首先，将包括具有简单整数比例的间距的子图案的布局图案提供给计算机系统。 然后将子图案分类为第一子图案和第二子图案。 之后，产生第一条纹图案和至少一个第二条纹图案。 第一条形图案的纵向边缘与第一子图案的纵向边缘对准，并且第一条纹图案具有相等的间距和宽度。 第二条纹图案的位置对应于空白图案的位置，第二条纹图案的间距或宽度不同于第一条纹图案的间距或宽度。 最后，将第一条纹图案和第二条纹图案输出到光掩模。

公开(公告)号：US20150206759A1

公开(公告)日：2015-07-23

申请号：US14159457

申请日：2014-01-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Chao Tsao ,  Lung-En Kuo ,  Chien-Ting Lin ,  Shih-Fang Tzou

IPC: H01L21/308 ,  H01L21/762 ,  H01L29/06

CPC classification number: H01L21/76224 ,  H01L21/0273 ,  H01L21/3086 ,  H01L21/31053 ,  H01L21/823431 ,  H01L21/823481 ,  H01L29/0653 ,  H01L29/0657 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/785

Abstract: The present invention provides a semiconductor structure including a substrate, at least one fin group and a plurality of sub-fin structures disposed on the substrate, wherein the fin group is disposed between two sub-fin structures, and a top surface of each sub-fin structure is lower than a top surface of the fin group; and a shallow trench isolation (STI) disposed in the substrate, wherein the sub-fin structures are completely covered by the shallow trench isolation.

Abstract translation: 本发明提供一种半导体结构，其包括基板，至少一个翅片组和设置在基板上的多个亚翅片结构，其中，翅片组设置在两个子鳍结构之间，并且每个子鳍结构的顶表面， 翅片结构低于翅片组的顶面; 以及设置在衬底中的浅沟槽隔离（STI），其中子鳍结构被浅沟槽隔离完全覆盖。

公开(公告)号：US09018066B2

公开(公告)日：2015-04-28

申请号：US14042224

申请日：2013-09-30

Applicant: United Microelectronics Corp.

Inventor： Yen-Liang Wu ,  Chung-Fu Chang ,  Yu-Hsiang Hung ,  Ssu-I Fu ,  Chien-Ting Lin ,  Shih-Fang Tzou

IPC: H01L21/336 ,  H01L21/28 ,  H01L29/66 ,  H01L21/311

CPC classification number: H01L21/31111 ,  H01L21/3086 ,  H01L21/31116 ,  H01L29/165 ,  H01L29/517 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

Abstract: A method of fabricating a semiconductor device structure is provided. The method includes the following step. A gate dielectric layer is formed on a substrate. A gate electrode is on the gate dielectric layer. The gate dielectric layer exposed by the gate electrode is treated. A first etching process is performed to remove at least a portion of the gate dielectric layer exposed by the gate electrode. A spacer is formed on the sidewall of the gate electrode. A second etching process is performed to form recesses in the substrate beside the gate electrode. Besides, during the first etching process and the second etching process, an etching rate of the treated gate dielectric layer is greater than an etching rate of the untreated gate dielectric layer.

Abstract translation: 提供一种制造半导体器件结构的方法。 该方法包括以下步骤。 在基板上形成栅极电介质层。 栅极电极位于栅极电介质层上。 处理由栅电极露出的栅介电层。 执行第一蚀刻工艺以去除由栅电极暴露的栅介质层的至少一部分。 在栅电极的侧壁上形成间隔物。 执行第二蚀刻工艺以在栅电极旁边的基板中形成凹部。 此外，在第一蚀刻工艺和第二蚀刻工艺期间，经处理的栅极电介质层的蚀刻速率大于未处理的栅极介电层的蚀刻速率。

公开(公告)号：US20140327055A1

公开(公告)日：2014-11-06

申请号：US13886382

申请日：2013-05-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Jun-Jie Wang ,  Po-Chao Tsao ,  Chia-Jui Liang ,  Shih-Fang Tzou ,  Chien-Ting Lin ,  Cheng-Guo Chen ,  Ssu-I Fu ,  Yu-Hsiang Hung ,  Chung-Fu Chang

IPC: H01L21/28 ,  H01L29/40

CPC classification number: H01L29/42364 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/513 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/7851

Abstract: A replacement gate process is disclosed. A substrate and a dummy gate structure formed on the substrate is provided, wherein the dummy gate structure comprises a dummy layer on the substrate, a hard mask layer on the dummy layer, spacers at two sides of the dummy layer and the hard mask layer, and a contact etch stop layer (CESL) covering the substrate, the spacers and the hard mask layer. The spacers and the CESL are made of the same material. Then, a top portion of the CESL is removed to expose the hard mask layer. Next, the hard mask layer is removed. Afterward, the dummy layer is removed to form a trench.

Abstract translation: 公开了替代浇口工艺。 提供了一种在基板上形成的基板和虚拟栅极结构，其中，虚设栅极结构包括基板上的虚设层，虚设层上的硬掩模层，虚设层两侧的间隔物和硬掩模层， 以及覆盖衬底，间隔物和硬掩模层的接触蚀刻停止层（CESL）。 垫片和CESL由相同的材料制成。 然后，去除CESL的顶部以露出硬掩模层。 接下来，去除硬掩模层。 之后，去除虚拟层以形成沟槽。