公开(公告)号：US08993433B2

公开(公告)日：2015-03-31

申请号：US13902977

申请日：2013-05-27

Applicant: United Microelectronics Corp.

Inventor： Chieh-Te Chen ,  Yu-Tsung Lai ,  Hsuan-Hsu Chen ,  Feng-Yi Chang ,  Chih-Sen Huang ,  Ching-Wen Hung

IPC: H01L21/4763 ,  H01L21/44 ,  H01L21/768

CPC classification number: H01L21/76816 ,  H01L21/76843 ,  H01L21/76895 ,  H01L21/76897 ,  H01L23/485

Abstract: The present invention provides a manufacturing method of a semiconductor device, at least containing the following steps: first, a substrate is provided, wherein a first dielectric layer is formed on the substrate, at least one metal gate is formed in the first dielectric layer and at least one source drain region (S/D region) is disposed on two sides of the metal gate, at least one first trench is then formed in the first dielectric layer, exposing parts of the S/D region. The manufacturing method for forming the first trench further includes performing a first photolithography process through a first photomask and performing a second photolithography process through a second photomask, and at least one second trench is formed in the first dielectric layer, exposing parts of the metal gate, and finally, a conductive layer is filled in each first trench and each second trench.

Abstract translation: 本发明提供一种半导体器件的制造方法，至少包括以下步骤：首先，提供基板，其中在基板上形成第一介电层，在第一介电层中形成至少一个金属栅极， 至少一个源极漏极区域（S / D区域）设置在金属栅极的两侧，然后在第一介电层中形成至少一个第一沟槽，暴露S / D区域的部分。 用于形成第一沟槽的制造方法还包括通过第一光掩模执行第一光刻工艺并通过第二光掩模执行第二光刻工艺，并且在第一电介质层中形成至少一个第二沟槽，暴露部分金属栅极 并且最后，在每个第一沟槽和每个第二沟槽中填充导电层。

公开(公告)号：US20140342553A1

公开(公告)日：2014-11-20

申请号：US13893349

申请日：2013-05-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chieh-Te Chen ,  Feng-Yi Chang ,  Hsuan-Hsu Chen ,  Yu-Tsung Lai ,  Chih-Sen Huang ,  Ching-Wen Hung

IPC: H01L21/768 ,  H01L21/283

CPC classification number: H01L21/76897 ,  H01L21/31144 ,  H01L21/76816

Abstract: According to one embodiment of the present invention, a method for forming a semiconductor structure having an opening is provided. First, a substrate is provided, wherein a first region and a second region are defined on the substrate and an overlapping area of the first region and the second region is defined as a third region. Then, a material layer is formed on the substrate. A first hard mask and a second hard mask are formed on the material layer. The first hard mask in the first region is removed to form a patterned first hard mask. The second hard mask in the third region is removed to form a patterned second hard mask. Lastly, the material layer is patterned by using the patterned second hard mask layer as a mask to form at least an opening in the third region only.

Abstract translation: 根据本发明的一个实施例，提供一种形成具有开口的半导体结构的方法。 首先，提供衬底，其中在衬底上限定第一区域和第二区域，并且将第一区域和第二区域的重叠区域定义为第三区域。 然后，在基板上形成材料层。 第一硬掩模和第二硬掩模形成在材料层上。 第一区域中的第一硬掩模被去除以形成图案化的第一硬掩模。 去除第三区域中的第二硬掩模以形成图案化的第二硬掩模。 最后，通过使用图案化的第二硬掩模层作为掩模来对材料层进行图案化，以仅在第三区域中形成至少一个开口。

公开(公告)号：US08853041B2

公开(公告)日：2014-10-07

申请号：US14182257

申请日：2014-02-17

Applicant: United Microelectronics Corp.

Inventor： Ching-Wen Hung

IPC: H01L29/66 ,  H01L29/51 ,  H01L21/8238 ,  H01L29/772 ,  H01L29/417 ,  H01L29/78

CPC classification number: H01L29/66575 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/41783 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/772 ,  H01L29/7848

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a region; forming a gate structure on the region of the substrate; forming a raised epitaxial layer in the substrate adjacent to two sides of the gate structure; covering a dielectric layer on the gate structure and the raised epitaxial layer; and using a planarizing process to partially remove the dielectric layer and the gate structure such that the surface of the gate structure is even with the surface of the raised epitaxial layer.

Abstract translation: 公开了半导体器件的制造方法。 该方法包括以下步骤：提供具有区域的衬底; 在所述基板的区域上形成栅极结构; 在所述衬底中邻近所述栅极结构的两侧形成凸起的外延层; 覆盖栅极结构和凸起的外延层上的介电层; 并且使用平坦化工艺来部分去除电介质层和栅极结构，使得栅极结构的表面与凸起的外延层的表面均匀。

公开(公告)号：US08802521B1

公开(公告)日：2014-08-12

申请号：US13909101

申请日：2013-06-04

Applicant: United Microelectronics Corp.

Inventor： Ching-Wen Hung ,  Chih-Sen Huang ,  Shih-Fang Hong

IPC: H01L21/336 ,  H01L29/06 ,  H01L21/762

CPC classification number: H01L21/76224 ,  H01L21/3086 ,  H01L29/6681 ,  H01L29/7851

Abstract: The present invention provides a method for forming a fin structure comprising the following steps: first, a substrate is provided and a plurality of fin structures, a plurality of first dummy fin structures and a plurality of second dummy fin structures are formed on the substrate; a first patterned photoresist is used as a hard mask to perform a first etching process to remove each first dummy fin structure; then a second patterned photoresist is used as a hard mask to perform a second etching process to remove each second dummy fin structure, wherein the pattern density of the first patterned photoresist is higher than the pattern density of the second patterned.

Abstract translation: 本发明提供一种形成翅片结构的方法，包括以下步骤：首先，提供基板，并在基板上形成多个翅片结构，多个第一虚拟翅片结构和多个第二虚拟翅片结构; 使用第一图案化的光致抗蚀剂作为硬掩模来执行第一蚀刻工艺以去除每个第一虚拟鳍结构; 然后使用第二图案化的光刻胶作为硬掩模来执行第二蚀刻工艺以去除每个第二虚拟鳍片结构，其中第一图案化光刻胶的图案密度高于第二图案化图案的图案密度。

公开(公告)号：US20140199837A1

公开(公告)日：2014-07-17

申请号：US13740289

申请日：2013-01-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Wen Hung ,  En-Chiuan Liou ,  Chih-Sen Huang ,  Po-Chao Tsao

IPC: H01L21/768

CPC classification number: H01L21/76816 ,  H01L21/28518 ,  H01L21/31144 ,  H01L21/76814 ,  H01L21/76855 ,  H01L23/485 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming a semiconductor structure having at least a contact plug includes the following steps. At first, at least a transistor and an inter-layer dielectric (ILD) layer are formed on a substrate, and the transistor includes a gate structure and two source/drain regions. Subsequently, a cap layer is formed on the ILD layer and on the transistor, and a plurality of openings that penetrate through the cap layer and the ILD layer until reaching the source/drain regions are formed. Afterward, a conductive layer is formed to cover the cap layer and fill the openings, and a part of the conductive layer is further removed for forming a plurality of first contact plugs, wherein a top surface of a remaining conductive layer and a top surface of a remaining cap layer are coplanar, and the remaining cap layer totally covers a top surface of the gate structure.

Abstract translation: 形成至少具有接触插塞的半导体结构的方法包括以下步骤。 首先，在衬底上形成至少一个晶体管和层间电介质（ILD）层，并且晶体管包括栅极结构和两个源极/漏极区域。 随后，在ILD层和晶体管上形成覆盖层，并且形成穿过覆盖层和ILD层的多个开口直到到达源/漏区。 之后，形成导电层以覆盖盖层并填充开口，并且进一步去除导电层的一部分以形成多个第一接触塞，其中剩余导电层的顶表面和顶表面 剩余的盖层是共面的，剩余的盖层完全覆盖栅极结构的顶表面。

公开(公告)号：US20240243073A1

公开(公告)日：2024-07-18

申请号：US18116812

申请日：2023-03-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Wen Hung ,  Jinn-Horng Lai ,  Yan-Zung Wang ,  Peng-Hsiu Chen ,  Su-Ming Hsieh

IPC: H01L23/552 ,  H01L23/522

CPC classification number: H01L23/552 ,  H01L23/5225 ,  H01L2223/66

Abstract: A radio-frequency (RF) device includes a main device on a substrate, a first port extending along a first direction adjacent to a first side of the main device, a second port extending along the first direction adjacent to a second side of the main device, a first shield structure adjacent to a third side of the main device, a second shield structure adjacent to a fourth side of the main device, a first connecting structure extending along a second direction to connect the first port and the main device, and a second connecting structure extending along the second direction to connect the second port and the main device.

公开(公告)号：US20240222355A1

公开(公告)日：2024-07-04

申请号：US18105888

申请日：2023-02-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Wen Hung ,  Peng-Hsiu Chen ,  Su-Ming Hsieh ,  Chun-Hsien Lin

IPC: H01L27/02 ,  H01L27/085 ,  H01L29/06 ,  H01L29/66 ,  H01L29/778

CPC classification number: H01L27/0207 ,  H01L27/085 ,  H01L29/0692 ,  H01L29/66462 ,  H01L29/7786

Abstract: The invention provides a layout pattern of a semiconductor cell, which comprises a substrate with a first L-shaped MESA region and a second L-shaped MESA region, wherein the shapes of the first L-shaped MESA region and the second L-shaped MESA region are mutually inverted by 180 degrees, a first high electron mobility transistor (HEMT) and a second high electron mobility transistor are located on the first L-shaped MESA region, and a third high electron mobility transistor and a fourth high electron mobility transistor are located on the second L-shaped MESA region.

公开(公告)号：US20240090341A1

公开(公告)日：2024-03-14

申请号：US18511974

申请日：2023-11-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Wen Hung ,  Ya-Sheng Feng

IPC: H10N50/80 ,  H01L21/768 ,  H10N50/01

CPC classification number: H10N50/80 ,  H01L21/76801 ,  H01L21/76838 ,  H10N50/01

Abstract: A method for fabricating semiconductor device includes the steps of: forming a first inter-metal dielectric (IMD) layer on a substrate; forming a metal interconnection in the first IMD layer; forming a bottom electrode layer and a pinned layer on the first IMD layer; forming a sacrificial layer on the pinned layer; patterning the sacrificial layer, the pinned layer, and the bottom electrode layer to form a first magnetic tunneling junction (MTJ); forming a second IMD layer around the first MTJ; removing the sacrificial layer to form a recess; forming a barrier layer and a free layer in the recess; forming a top electrode layer on the free layer; and patterning the top electrode layer and the free layer to form a second MTJ.

公开(公告)号：US20230299166A1

公开(公告)日：2023-09-21

申请号：US18201769

申请日：2023-05-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Kuang Hsieh ,  Shih-Hung Tsai ,  Ching-Wen Hung ,  Chun-Hsien Lin

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/66 ,  H01L29/16 ,  H01L29/45 ,  H01L29/786

CPC classification number: H01L29/42392 ,  H01L29/0673 ,  H01L29/66045 ,  H01L29/1606 ,  H01L29/45 ,  H01L29/78696

Abstract: A method for fabricating a nanowire transistor includes the steps of first forming a nanowire channel structure on a substrate, in which the nanowire channel structure includes first semiconductor layers and second semiconductor layers alternately disposed over one another. Next, a gate structure is formed on the nanowire channel structure and then a source/drain structure is formed adjacent to the gate structure, in which the source/drain structure is made of graphene.

公开(公告)号：US11581191B2

公开(公告)日：2023-02-14

申请号：US17241704

申请日：2021-04-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Wen Hung

IPC: H01L21/3105 ,  H01L27/088 ,  H01L21/8234 ,  H01L23/00 ,  H01L23/522 ,  H01L27/06

Abstract: A semiconductor device structure and a manufacturing method thereof are provided. The semiconductor device structure includes a semiconductor substrate having an active component region and a non-active component region, a first dielectric layer, a second dielectric layer, high resistivity metal segments, dummy stacked structures and a metal connection structure. The high resistivity metal segments are formed in the second dielectric layer and located in the non-active component region. The dummy stacked structures are located in the non-active component region, and at least one dummy stacked structure penetrates through the first dielectric layer and the second dielectric layer and is located between two adjacent high resistivity metal segments. The metal connection structure is disposed on the second dielectric layer, and the high resistivity metal segments are electrically connected to one another through the metal connection structure.