公开(公告)号：WO2014155348A1

公开(公告)日：2014-10-02

申请号：PCT/IB2014/060249

申请日：2014-03-28

Applicant: STMICROELECTRONICS S.R.L.

Inventor： PAGANI, Alberto ,  MURARI, Bruno

IPC: G01N27/22

CPC classification number: G01N27/223 ,  G01N17/04

Abstract: An integrated electronic device 1 for detecting at least one parameter related to humidity and/or presence of water and/or acidity/basicity of an environment surrounding the device is described. Such device 1 comprises a separation layer 14 from the surrounding environment, comprising at least one portion of insulating material 14, and further comprises a first conductive member 11 and a second conductive member 12, made of an electrically conductive material, arranged inside the separation layer 14, with respect to the surrounding environment, and separated from the surrounding environment by the separation layer 14. The device 1 also comprises a measurement module 15, having two measurement terminals 151, 152, electrically connected with the first 11 and the second 12 conductive members, respectively; the measurement module 15 is configured to provide an electric potential difference between the first 11 and the second 12 conductive members. The device 1 further comprises electrode means 13, configured to act as an electrode, arranged outside of the separation layer 14, with respect to the first 11 and the second 12 conductive members; the electrode means 13 are arranged so as to form, with the first 11 and the second 12 conductive members, an electromagnetic circuit having an electromagnetic circuit overall impedance variable based upon the exposure to environmental conditions with a variable level of humidity and/or acidity/basicity. The measurement module 15 is configured to measure the electromagnetic circuit overall impedance, which is present between the measurement terminals 151, 152, and to determine the at least one parameter to be detected, based on the overall impedance measured.

Abstract translation: 描述了用于检测与湿度和/或水的存在和/或设备周围环境的酸度/碱度相关的至少一个参数的集成电子设备1。 这种装置1包括与周围环境的分离层14，其包括绝缘材料14的至少一部分，并且还包括布置在分离层内部的由导电材料制成的第一导电构件11和第二导电构件12 14，相对于周围环境，并且通过分离层14与周围环境分离。装置1还包括测量模块15，其具有两个测量端子151,152，与第一11和第二导电12电连接 成员分别; 测量模块15被配置为提供第一11和第二导电构件12之间的电位差。 装置1还包括电极装置13，其被配置为相对于第一11和第二导电构件作为布置在分离层14外侧的电极; 电极装置13被布置成与第一11和第二12导电构件形成电磁电路，该电磁电路具有基于暴露于具有可变湿度和/或酸度/湿度的环境条件的总体阻抗变化， 碱性。 测量模块15被配置为基于测量的总阻抗来测量存在于测量端子151,152之间的电磁回路总阻抗，并且确定要检测的至少一个参数。

公开(公告)号：WO2014049537A1

公开(公告)日：2014-04-03

申请号：PCT/IB2013/058852

申请日：2013-09-25

Applicant: STMICROELECTRONICS S.R.L.

Inventor： PAGANI, Alberto ,  ZIGLIOLI, Federico Giovanni

IPC: H05K1/02

CPC classification number: G01L1/005 ,  G01N33/38 ,  H05K1/0239 ,  H05K1/0278 ,  H05K1/189 ,  H05K2201/09081 ,  H05K2201/10098 ,  H05K2201/10151 ,  Y10T156/1051

Abstract: A planar electric circuit board may include a planar support of a foldable material defining a base surface and wings coupled to the base surface along respective folding lines so that the wings, when folded along the folding lines, are erected with respect to the base surface and remain in that position. An auxiliary circuit is on the planar support and may include pairs of capacitive coupling plates defined on the wings and on the base surface, and electric communication lines coupled to corresponding ones of the pairs of capacitive coupling plates.

Abstract translation: 平面电路板可以包括限定基部表面的可折叠材料的平面支撑件和沿着各个折叠线连接到基座表面的翼片，使得当沿着折叠线折叠时的翼片相对于基部表面竖立，并且 保持在这个位置。 辅助电路在平面支撑件上，并且可以包括限定在翼部和基部表面上的成对的电容耦合板，以及耦合到成对的电容耦合板中的对应的电气通信线。

公开(公告)号：WO2013174946A1

公开(公告)日：2013-11-28

申请号：PCT/EP2013/060669

申请日：2013-05-23

Applicant: STMICROELECTRONICS S.R.L.

Inventor： PAGANI, Alberto ,  MURARI, Bruno ,  ZIGLIOLI, Federico Giovanni ,  RONCHI, Marco ,  RICOTTI, Giulio

IPC: G01D11/24 ,  G01M5/00

CPC classification number: G01D11/245 ,  B28B23/0031 ,  G01K17/00 ,  G01L1/18 ,  G01M5/00 ,  G01N33/383

Abstract: A package (15) for devices (100) insertable into a solid structure (300) for detecting and monitoring one or more local parameters is described. The package (15) is made of a building material formed of particles of micrometric or sub-micrometric dimensions. A device (100) for detecting and monitoring one or more local parameters within a solid structure is further described. The device (100) comprises an integrated detection module (1), having at least one integrated sensor (10), and a package (15), having the above-mentioned characteristics, so arranged as to coat at least one portion of the device (100), comprising the integrated detection module (1). A method for manufacturing the device (100), and a system (200) for monitoring parameters in a solid structure (300), comprising such a device (100), are also described.

Abstract translation: 描述了可插入到用于检测和监视一个或多个局部参数的实体结构（300）中的装置（100）的封装（15）。 包装（15）由由微米或亚微米尺寸的颗粒形成的建筑材料制成。 进一步描述用于检测和监视固体结构内的一个或多个局部参数的装置（100）。 装置（100）包括具有至少一个集成传感器（10）的集成检测模块（1）和具有上述特征的封装（15），其被布置成涂覆该装置的至少一部分 （100），包括所述集成检测模块（1）。 还描述了用于制造装置的方法（100），以及用于监视包括这种装置（100）的实体结构（300）中的参数的系统（200）。

公开(公告)号：WO2013097938A1

公开(公告)日：2013-07-04

申请号：PCT/EP2012/005311

申请日：2012-12-20

Applicant: STMICROELECTRONICS S.R.L.

Inventor： VENEROSO, Amedeo ,  VARONE, Francesco ,  FRALLICCIARDI, Paolo

IPC: H01Q1/38 ,  H01Q1/22 ,  H04B1/38 ,  G06K19/077

CPC classification number: H01Q1/38 ,  H01Q1/2208

Abstract: The present invention relates to a flexible antenna for NFC communication with SIM card of a mobile device, comprising a RF pad for establishing radio communication with another device. Each projection extending from the RF pad comprises on its end a SIM pad with a different orientation with respect to the orientation of the other SIM pads on the other projections.

Abstract translation: 本发明涉及一种用于与移动设备的SIM卡进行NFC通信的柔性天线，包括用于与另一设备建立无线电通信的RF焊盘。 从RF焊盘延伸的每个突起在其端部上包括相对于其它突起上的其它SIM焊盘的取向具有不同取向的SIM焊盘。

公开(公告)号：WO2011079882A1

公开(公告)日：2011-07-07

申请号：PCT/EP2010/005931

申请日：2010-09-29

Applicant: STMICROELECTRONICS S.R.L. ,  ROSSI, Sandro ,  RICCIARDO, Antonio ,  GHISU, Davide Ugo

Inventor： ROSSI, Sandro ,  RICCIARDO, Antonio ,  GHISU, Davide Ugo

IPC: H03K17/0416 ,  H03K17/06 ,  H03K17/16 ,  H03K17/687 ,  B06B1/02

CPC classification number: H03K17/063 ,  B06B1/0215 ,  H03K17/04163 ,  H03K17/162 ,  H03K17/6872

Abstract: A switching circuit (30) is described being inserted between a connection terminal (Xdcr) and an output terminal (LVout) of a transmission channel (1) and of the type comprising at least one first and one second switching transistor (MSW1, MSW2) which are high voltage MOS transistors of complementary type inserted, in series to each other and by having respective equivalent or body diodes (DSW1, DSW2) in anti-series, between the connection terminal (Xdcr) and the output terminal (LVout). Advantageously according to the invention, the switching circuit comprises at least one bootstrap circuit (31) connected to respective first and second control terminals (XG1, XG2) of these at least one first and one second switching transistor (MSW1, MSW2), as well as to respective first and second voltage references (VDD_P, VDD_M) and having values of parasite capacities between these first and second control terminals (XG1, XG2) and at least one first and one second bootstrap node (XB1, XB2) of at least one order of magnitude lower with respect to the gate-source capacities (Csw1, Csw2) of these at least one first and one second switching transistor (MSW1, MSW2).

Abstract translation: 描述了切换电路（30）被插入在传输通道（1）的连接端子（Xdcr）和输出端子（LVout）之间，并且包括至少一个第一和第二开关晶体管（MSW1，MSW2）的类型， （Xdcr）和输出端子（LVout）之间具有反相串联的相应的等效或体二极管（DSW1，DSW2）。 有利地，根据本发明，切换电路包括连接到这些至少一个第一和第二开关晶体管（MSW1，MSW2）的相应的第一和第二控制端子（XG1，XG2）的至少一个自举电路（31），以及 对于相应的第一和第二参考电压（VDD_P，VDD_M），并且具有这些第一和第二控制端子（XG1，XG2）之间的寄生电容值和至少一个第一和第二引导节点（XB1，XB2） 相对于这些至少一个第一和第二开关晶体管（MSW1，MSW2）的栅极 - 源极电容（Csw1，Csw2）的数量级下降。

公开(公告)号：WO2011079880A1

公开(公告)日：2011-07-07

申请号：PCT/EP2010/005929

申请日：2010-09-29

Applicant: STMICROELECTRONICS S.R.L. ,  BOTTAREL, Valeria ,  RICOTTI, Giulio ,  QUAGLIA, Fabio ,  GIOVANNONE, Juri

Inventor： BOTTAREL, Valeria ,  RICOTTI, Giulio ,  QUAGLIA, Fabio ,  GIOVANNONE, Juri

IPC: H03K17/693 ,  H03K17/74 ,  H03K17/06 ,  H03K17/687 ,  B06B1/02 ,  H03K17/0812

CPC classification number: H03K17/693 ,  B06B1/0215 ,  H03K17/06 ,  H03K17/08122 ,  H03K17/6872 ,  H03K17/74

Abstract: A low voltage isolation switch (1) is described, inserted between an input terminal (HVout) suitable for receiving a high voltage signal (IM) and an output terminal (pzt) suitable for transmitting this high voltage signal (IM) to a load (PZ) of the type comprising at least one driving block (5) being inserted between a first and a second voltage reference (Vss, -Vss) and comprising a first driving transistor (M1), inserted, in series to a first driving diode (D1), between the first voltage reference (Vss) and a first driving central circuit node (Xd) and a second driving transistor (M2), in turn inserted, in series with a second driving diode (D2), between the driving central circuit node (Xd) and the second supply voltage reference (-Vss) as well as a control transistor (MD) connected across a diode block (7) comprising at least one first and one second transmission diode (DN1, DN2), connected in antiparallel, i.e. by having the anode terminal of the first diode connected to the cathode terminal of the second one and vice versa, between the input (HVout) and output (pzt) terminals of the low voltage isolation switch (1), this control transistor (MD) having a control terminal connected to the driving central circuit node (Xd) through a low voltage decoupling block (6), in turn inserted between a first and a second substrate terminal (SS1, SS2) and also comprising a first and a second parasite capacitive element (Par1, Par2) connected to these first and second substrate terminals (SS1, SS2) as well as comprising at least one first decoupling transistor (M3) and one second decoupling transistor inserted (M4), being in parallel to each other and having control terminals connected to the first and second parasite capacitive elements (Par1, Par2), respectively.

Abstract translation: 描述了将低电压隔离开关（1）插入适于接收高电压信号（IM）的输入端（HVout）和适于将该高电压信号（IM）发送到负载的输出端（pzt）之间 PZ），其包括插入在第一和第二参考电压（Vss，-Vss）之间的至少一个驱动块（5），并且包括与第一驱动二极管串联插入的第一驱动晶体管（M1） D1），在第一电压基准（Vss）和第一驱动中心电路节点（Xd）和第二驱动晶体管（M2）之间，与第二驱动二极管（D2）串联插入驱动中心电路 节点（Xd）和第二电源电压参考（-Vss）以及连接在二极管块（7）之间的控制晶体管（MD），二极管块（7）包括至少一个第一和第二传输二极管（DN1，DN2），反相并联 即通过使第一二极管的阳极端子连接到阴极 在低电压隔离开关（1）的输入（HVout）和输出（pzt）端子之间，该控制晶体管（MD）具有连接到驱动中心电路节点的控制端（ Xd）通过低电压去耦块（6）进而插入在第一和第二衬底端子（SS1，SS2）之间，并且还包括连接到这些第一和第二衬底端子的第一和第二寄生电容元件（Par1，Par2） 衬底端子（SS1，SS2）以及包括彼此并联并具有连接到第一和第二寄生电容元件的控制端子的至少一个第一去耦晶体管（M3）和一个第二去耦晶体管（M4） Par1，Par2）。

公开(公告)号：WO2010028836A1

公开(公告)日：2010-03-18

申请号：PCT/EP2009/006594

申请日：2009-09-10

Applicant: STMICROELECTRONICS S.R.L. ,  COZZI, Pier, Giorgio ,  ZOLI, Luca ,  BRAMANTI, Alessandro, Paolo

Inventor： COZZI, Pier, Giorgio ,  ZOLI, Luca ,  BRAMANTI, Alessandro, Paolo

IPC: C07F17/02 ,  G06N99/00

CPC classification number: G06N99/002 ,  B82Y10/00 ,  C07F17/02

Abstract: Bistable carbazole compounds of formula (I) are described, wherein M is Fe, Co, Ru or Os, preferably Fe, useful as basic functional units for computing systems based on the QCA (Quantum Cellular Automata) paradigm; a process for their preparation is also described.

Abstract translation: 描述了式（I）的双稳态咔唑化合物，其中M是Fe，Co，Ru或Os，优选Fe，可用作基于QCA（Quantum Cellular Automata）范式的计算系统的基本功能单元; 还描述了其制备方法。

公开(公告)号：WO2008023395A1

公开(公告)日：2008-02-28

申请号：PCT/IT2006/000628

申请日：2006-08-25

Applicant: STMICROELECTRONICS S.R.L. ,  ZAMPROGNO, Marco ,  NICOLLINI, Germano ,  MINUTI, Alberto

Inventor： ZAMPROGNO, Marco ,  NICOLLINI, Germano ,  MINUTI, Alberto

IPC: H03F3/00

CPC classification number: H03F1/3211 ,  H03F3/005 ,  H03F3/45475 ,  H03F3/45977 ,  H03F2203/45101 ,  H03F2203/45136 ,  H03F2203/45212 ,  H03F2203/45514

Abstract: An integrated buffer device (2) for a switched capacity circuit is described, comprising: - a buffer (7) having an output (OUT) for an output voltage dependent upon an input voltage (VIN) that can be supplied by a source (1) to the buffer device; - a capacitative switching component (C I ) that can be switched between a first and second condition in which it is connected, respectively, to the source and to the buffer to transfer the input voltage onto the output; said component being provided with a terminal (N2) having an associated stray capacity (C pi ). The device also comprises a charging and discharging device (SW CPIR , SW G ) configured to pre- charge the stray capacity at a reference voltage (REFM) before taking up the second condition and to pre-discharge the stray capacity before taking up the first condition.

Abstract translation: 描述了一种用于开关容量电路的集成缓冲器件（2），包括： - 缓冲器（7），其具有输出电压（OUT），该输出电压取决于可由源极（1）提供的输入电压（VIN） ）到缓冲装置; - 可以分别在其连接的第一和第二状态之间切换到电源和电容缓冲器以将输入电压传送到输出端的电容性开关部件（C SUB） 所述部件设置有具有相关联的杂散能力（C P1）的端子（N2）。 该装置还包括一个充电和放电装置（SW＆lt; CPIR＆gt;，＆lt;＆gt; G＆gt;），其被配置为在占用第二个参考电压之前对参考电压（REFM）预充电杂散容量 条件，并且在摄取第一个条件之前预先排出杂散容量。

公开(公告)号：WO2007148358A1

公开(公告)日：2007-12-27

申请号：PCT/IT2006/000485

申请日：2006-06-23

Applicant: STMICROELECTRONICS S.R.L. ,  MAGNI, Pierangelo ,  BRIOSCHI, Roberto

Inventor： MAGNI, Pierangelo ,  BRIOSCHI, Roberto

IPC: B01L3/00

CPC classification number: B01L3/502707 ,  B01L2200/027 ,  B01L2200/10 ,  B01L2300/043 ,  B01L2300/0609 ,  B01L2300/0867 ,  B01L2300/123 ,  B01L2300/1805 ,  B01L2400/0481 ,  B01L2400/0622 ,  B01L2400/0638 ,  B01L2400/0644 ,  Y10T436/25 ,  Y10T436/2575

Abstract: In a microfluidic assembly (20), a microfluidic device (I1) is provided with a body (4) in which at least a first inlet (7) for loading a fluid to analyse and a buried area (8) in fluidic communication with the first inlet (7) are defined. An analysis chamber (10') is in fluidic communication with the buried area (8) and an interface cover (23) is coupled in a fluid-tight manner above the microfluidic device (I1) . The interface cover (23) is provided with a sealing portion (35) in correspondence to the analysis chamber (10')/ adapted to assume a first configuration, at rest, in which it leaves the analysis chamber (10') open, and a second configuration, as a consequence of a stress, in which it closes in a fluid-tight manner the same analysis chamber.

Abstract translation: 在微流体组件（20）中，微流体装置（I1）设置有主体（4），其中至少第一入口（7）用于装载待分析的流体和与该流体相通的埋入区域（8） 定义第一入口（7）。 分析室（10'）与掩埋区域（8）流体连通，并且界面盖（23）以流体密封的方式联接在微流体装置（I1）上方。 接口盖（23）设置有与分析室（10'）对应的适于呈现静止状态的第一配置（其离开分析室10'）的密封部分（35），以及 作为应力的结果的第二构造，其以不流体密封的方式封闭相同的分析室。

公开(公告)号：WO2007113878A1

公开(公告)日：2007-10-11

申请号：PCT/IT2006/000229

申请日：2006-04-06

Applicant: STMICROELECTRONICS S.R.L. ,  RIVA, Caterina ,  MURARI, Bruno ,  FRATTINI, Giovanni

Inventor： RIVA, Caterina ,  MURARI, Bruno ,  FRATTINI, Giovanni

IPC: G11B9/00

CPC classification number: G11B9/1409 ,  B82Y10/00 ,  G11B9/14

Abstract: Described herein is a process for manufacturing an interaction structure for a storage medium, which envisages forming a first interaction head provided with a first conductive region having a sub-lithographic smaller dimension (W 1 ). The step of forming a first interaction head (7) envisages: forming on a surface (14) a first delimitation region (15) having a side wall; depositing a conductive portion (16b) having a deposition thickness substantially matching the sub- lithographic smaller dimension (W 1 ) on the side wall; and then defining the conductive portion. The sub- lithographic smaller dimension (W 1 ) is between 1 and 50 nm, preferably 20 nm.

Abstract translation: 这里描述的是用于制造用于存储介质（4）的相互作用结构（6）的方法，其设想形成具有第二导电区域（22）的第一相互作用头部（7），所述第一导电区域具有次光刻尺寸较小（Wi） 。 形成第一相互作用头（7）的步骤设想：在表面（14）上形成具有侧壁（15b）的第一限定区域（15）; 在所述侧壁（15b）上沉积具有基本上与所述亚光刻较小尺寸（Wi）匹配的沉积厚度的导电部分（16b）; 然后限定导电部分。 亚光刻尺寸较小（Wi）在1至50nm之间，优选20nm。