公开(公告)号：WO2007042336A3

公开(公告)日：2007-04-19

申请号：PCT/EP2006/064298

申请日：2006-07-14

Applicant: STMicroelectronics S.r.l. ,  COMBI, Chantal ,  VIGNA, Benedetto ,  ZIGLIOLI, Federico Giovanni ,  BALDO, Lorenzo ,  MAGUGLIANI, Manuela ,  LASALANDRA, Ernesto ,  RIVA, Caterina

Inventor： COMBI, Chantal ,  VIGNA, Benedetto ,  ZIGLIOLI, Federico Giovanni ,  BALDO, Lorenzo ,  MAGUGLIANI, Manuela ,  LASALANDRA, Ernesto ,  RIVA, Caterina

IPC: B81B7/02 ,  B81B7/00

Abstract: In a substrate-level assembly (22), a device substrate (20) of semiconductor material has a top face (20a) and houses a first integrated device (1; 16), in particular provided with a buried cavity (3), formed within the device substrate (20), and with a membrane (4), suspended over the buried cavity (3) in the proximity of the top face (20a). A capping substrate (21) is coupled to the device substrate (20) above the top face (20a) so as to cover the first integrated device (1; 16), in such a manner that a first empty space (25) is provided above the membrane (4). Electrical-contact elements (28a, 28b) electrically connect the integrated device (1; 16) with the outside of the substrate-level assembly (22). In one embodiment, the device substrate (20) integrates at least a further integrated device (1', 10) provided with a respective membrane (4'); and a further empty space (25'), fluidically isolated from the first empty space (25), is provided over the respective membrane (4') of the further integrated device (1', 10).

公开(公告)号：WO2014049537A1

公开(公告)日：2014-04-03

申请号：PCT/IB2013/058852

申请日：2013-09-25

Applicant: STMICROELECTRONICS S.R.L.

Inventor： PAGANI, Alberto ,  ZIGLIOLI, Federico Giovanni

IPC: H05K1/02

CPC classification number: G01L1/005 ,  G01N33/38 ,  H05K1/0239 ,  H05K1/0278 ,  H05K1/189 ,  H05K2201/09081 ,  H05K2201/10098 ,  H05K2201/10151 ,  Y10T156/1051

Abstract: A planar electric circuit board may include a planar support of a foldable material defining a base surface and wings coupled to the base surface along respective folding lines so that the wings, when folded along the folding lines, are erected with respect to the base surface and remain in that position. An auxiliary circuit is on the planar support and may include pairs of capacitive coupling plates defined on the wings and on the base surface, and electric communication lines coupled to corresponding ones of the pairs of capacitive coupling plates.

Abstract translation: 平面电路板可以包括限定基部表面的可折叠材料的平面支撑件和沿着各个折叠线连接到基座表面的翼片，使得当沿着折叠线折叠时的翼片相对于基部表面竖立，并且 保持在这个位置。 辅助电路在平面支撑件上，并且可以包括限定在翼部和基部表面上的成对的电容耦合板，以及耦合到成对的电容耦合板中的对应的电气通信线。

公开(公告)号：WO2013174946A1

公开(公告)日：2013-11-28

申请号：PCT/EP2013/060669

申请日：2013-05-23

Applicant: STMICROELECTRONICS S.R.L.

Inventor： PAGANI, Alberto ,  MURARI, Bruno ,  ZIGLIOLI, Federico Giovanni ,  RONCHI, Marco ,  RICOTTI, Giulio

IPC: G01D11/24 ,  G01M5/00

CPC classification number: G01D11/245 ,  B28B23/0031 ,  G01K17/00 ,  G01L1/18 ,  G01M5/00 ,  G01N33/383

Abstract: A package (15) for devices (100) insertable into a solid structure (300) for detecting and monitoring one or more local parameters is described. The package (15) is made of a building material formed of particles of micrometric or sub-micrometric dimensions. A device (100) for detecting and monitoring one or more local parameters within a solid structure is further described. The device (100) comprises an integrated detection module (1), having at least one integrated sensor (10), and a package (15), having the above-mentioned characteristics, so arranged as to coat at least one portion of the device (100), comprising the integrated detection module (1). A method for manufacturing the device (100), and a system (200) for monitoring parameters in a solid structure (300), comprising such a device (100), are also described.

Abstract translation: 描述了可插入到用于检测和监视一个或多个局部参数的实体结构（300）中的装置（100）的封装（15）。 包装（15）由由微米或亚微米尺寸的颗粒形成的建筑材料制成。 进一步描述用于检测和监视固体结构内的一个或多个局部参数的装置（100）。 装置（100）包括具有至少一个集成传感器（10）的集成检测模块（1）和具有上述特征的封装（15），其被布置成涂覆该装置的至少一部分 （100），包括所述集成检测模块（1）。 还描述了用于制造装置的方法（100），以及用于监视包括这种装置（100）的实体结构（300）中的参数的系统（200）。

公开(公告)号：EP3780074A3

公开(公告)日：2021-06-02

申请号：EP20191180.7

申请日：2020-08-14

Applicant: STMicroelectronics S.r.l.

Inventor： ZIGLIOLI, Federico Giovanni ,  PINTUS, Alberto ,  DERAI, Michele ,  MAGNI, Pierangelo

IPC: H01L21/56 ,  H01L21/60 ,  H01Q1/22 ,  H01L23/552 ,  H01L23/367 ,  H01L23/31

Abstract: A method of manufacturing semiconductor devices, such as integrated circuits comprises:
- providing a support surface (10),
- arranging one or more semiconductor dice (12) on the support surface (10),
- molding laser direct structuring (LDS) material (14) onto the support surface (10) having the semiconductor die/dice (12) arranged thereon,
- laser beam processing (L) the laser direct structuring material (14) molded onto the support surface (10) having the semiconductor die/dice (12) arranged thereon to provide electrically conductive formations (16) for the semiconductor die/dice (12) arranged on the support surface, and
- separating from the support surface (10) the semiconductor die/dice (12) provided with said electrically-conductive formations (16).

公开(公告)号：EP3832701A1

公开(公告)日：2021-06-09

申请号：EP20210546.6

申请日：2020-11-30

Applicant: STMicroelectronics S.r.l.

Inventor： ZIGLIOLI, Federico Giovanni ,  PINTUS, Alberto ,  MAGNI, Pierangelo

IPC: H01L21/48 ,  H01L23/498 ,  H01L23/538

Abstract: A method of manufacturing semiconductor devices (10) comprises:
- providing a plastic material substrate (100) having at least one die mounting location (102) for a semiconductor die (104),
- forming metallic traces (108a, 108b) on selected areas of the plastic material substrate (100), wherein the metallic traces (108a, 108b) provide electrically-conductive paths for coupling to the semiconductor die (104),
- attaching the semiconductor die (104) onto the at least one die mounting location (102),
- bonding the semiconductor die (104) attached onto the at least one die mounting location (102) to selected ones of the metallic traces (108a, 108b) formed on the plastic material substrate (100),
- molding package material (110) onto the semiconductor die (104) attached onto the at least one die mounting location (102).

公开(公告)号：EP3780074A2

公开(公告)日：2021-02-17

申请号：EP20191180.7

申请日：2020-08-14

Applicant: STMicroelectronics S.r.l.

Inventor： ZIGLIOLI, Federico Giovanni ,  PINTUS, Alberto ,  DERAI, Michele ,  MAGNI, Pierangelo

IPC: H01L21/56 ,  H01L21/60 ,  H01Q1/22 ,  H01L23/552 ,  H01L23/36

Abstract: A method of manufacturing semiconductor devices, such as integrated circuits comprises:
- providing a support surface (10),
- arranging one or more semiconductor dice (12) on the support surface (10),
- molding laser direct structuring (LDS) material (14) onto the support surface (10) having the semiconductor die/dice (12) arranged thereon,
- laser beam processing (L) the laser direct structuring material (14) molded onto the support surface (10) having the semiconductor die/dice (12) arranged thereon to provide electrically conductive formations (16) for the semiconductor die/dice (12) arranged on the support surface, and
- separating from the support surface (10) the semiconductor die/dice (12) provided with said electrically-conductive formations (16).

公开(公告)号：EP1945561A2

公开(公告)日：2008-07-23

申请号：EP06777802.7

申请日：2006-07-14

Applicant: STMicroelectronics S.r.l.

Inventor： COMBI, Chantal ,  VIGNA, Benedetto ,  ZIGLIOLI, Federico Giovanni ,  BALDO, Lorenzo ,  MAGUGLIANI, Manuela ,  LASALANDRA, Ernesto ,  RIVA, Caterina

IPC: B81B7/02

CPC classification number: B81B7/0061 ,  B81B7/02 ,  B81B2201/0235 ,  B81B2201/0264 ,  B81C1/0023 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2924/1461 ,  H01L2924/3025 ,  H04R1/04 ,  H04R19/005 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A substrate-level assembly having a device substrate of semiconductor material with a top face and housing a first integrated device, including a buried cavity formed within the device substrate, and with a membrane suspended over the buried cavity in the proximity of the top face. A capping substrate is coupled to the device substrate above the top face so as to cover the first integrated device in such a manner that a first empty space is provided above the membrane. Electrical-contact elements electrically connect the integrated device with the outside of the substrate-level assembly. In one embodiment, the device substrate integrates at least a further integrated device provided with a respective membrane, and a further empty space, fluidly isolated from the first empty space, is provided over the respective membrane of the further integrated device.

Abstract translation: 具有A衬底级组件的半导体材料的器件衬底具有顶面和外壳的第一集成器件，包括器件衬底内形成的掩埋空腔，并用悬浮在在顶面的接近掩埋空腔的膜。 甲封盖衬底耦合到所述顶面之上的器件衬底，以便覆盖所述第一集成器件在寻求做的膜上方提供第一空白空间的方式。 电接触元件电连接与所述衬底级组件的外部集成器件。 在一个实施例中，器件衬底至少集成设置有respectivement膜的进一步集成器件，和另外的空的空间，从所述第一空的空间流体地隔离，则在进一步的集成器件的respectivement膜提供。