公开(公告)号：US20210141661A1

公开(公告)日：2021-05-13

申请号：US16680915

申请日：2019-11-12

Applicant: Silicon Laboratories Inc.

Inventor： Jean-François Deschenes

IPC: G06F9/46 ,  G06F9/48 ,  G06F9/30

Abstract: A system and method of minimizing the context saved when the processing unit is disclosed. The kernel attempts to save time and memory by reducing or eliminating the amount of context that is saved or restored in certain situations. Specifically, if there is no currently executing, the kernel does not save any context before switching to another task. Similarly, if there is no new task to execute, the kernel does not restore any context before making the context switch. Rather, the kernel applies a lightweight context. In some embodiments, the idle context uses the ISR stack rather than having a dedicated stack. This system and method reduces the time required for certain context switches and also saves memory.

公开(公告)号：US20210135692A1

公开(公告)日：2021-05-06

申请号：US16886645

申请日：2020-05-28

Applicant: Silicon Laboratories Inc.

Inventor： Hendricus de Ruijter ,  Güner Arslan ,  Wentao Li ,  Michael Wu

IPC: H04B1/00 ,  H04B1/16 ,  H04L27/00

Abstract: An apparatus comprises an RF receiver for receiving an RF signal. The RF receiver includes front-end circuitry to generate a first down-converted signal, and a plurality of signal detectors to generate a corresponding plurality of detection signals from signals derived from the down-converted signal. The RF receiver further includes a controller to provide at least one control signal to the front-end circuitry based on the plurality of detection signals.

公开(公告)号：US10972077B2

公开(公告)日：2021-04-06

申请号：US16912652

申请日：2020-06-25

Applicant: Silicon Laboratories Inc.

Inventor： Steffen Skaug ,  Vitor Pereira ,  Arup Mukherji

IPC: G01R29/26 ,  G06F1/04 ,  H03B5/20 ,  H03K3/013

Abstract: An integrated circuit including a functional circuit including at least one swapping circuit node, multiple duplicate electronic circuits, and a switch circuit. The duplicate electronic circuits are integrated in close proximity with each other each including at least one electronic device that is susceptible to RTN. The switch circuit electrically couples a different selected subset of at least one of the duplicate electronic circuits to the at least one swapping circuit node for each of successive switching states during operation of the functional circuit. A method of reducing noise including selecting a subset of the duplicate electronic circuits, electrically coupling the selected duplicate electronic devices to at least one swapping circuit node of a functional circuit, and repeating the selecting and electrically coupling in successive switching states during operation of the functional circuit for different subsets of the duplicate electronic circuits.

公开(公告)号：US20210080993A1

公开(公告)日：2021-03-18

申请号：US16569991

申请日：2019-09-13

Applicant: Silicon Laboratories Inc.

Inventor： Thomas Saroshan David

IPC: G06F1/08 ,  H03K17/687

Abstract: A configurable clock buffer including first and second buffers and isolation circuitry. The first buffer has an input coupled to a clock input node and has an output coupled to a clock output node. The second buffer has an input coupled to an intermediate input node and has an output coupled to an intermediate output node. The isolation circuitry is responsive to at least one mode signal, in which it electrically couples the intermediate input node to the clock input node and electrically couples the intermediate output node to the clock output node when the at least one mode signal is in a first state, and in which it electrically couples the intermediate input node to a static node and electrically isolates the intermediate output node from the clock output node when the at least one mode signal is in a second state.

公开(公告)号：US10917081B1

公开(公告)日：2021-02-09

申请号：US16815435

申请日：2020-03-11

Applicant: Silicon Laboratories Inc.

Inventor： Long Nguyen ,  Ion C. Tesu ,  Michael L. Duffy ,  John N. Wilson

IPC: H03K17/08 ,  H03K17/0812 ,  H02M1/08 ,  H03K17/18 ,  H03K17/082 ,  H03K17/081 ,  H03K17/16

Abstract: An apparatus controls a high-power drive device external to a package of a gate driver circuit. A first circuit charges the control node over a first length of time in response to a first signal through the first node indicating an absence of a fault condition and a first level of a control signal. A second circuit discharges the control node over a second length of time in response to a second signal through the second node indicating the absence of the fault condition and a second level of a control signal. A third circuit includes a current amplifier and is configured as a soft shutdown path to discharge the control node over a third length of time in response to the first signal through the first node indicating a presence of the fault condition. The third length of time is different from the second length of time.

公开(公告)号：US10911129B1

公开(公告)日：2021-02-02

申请号：US16711824

申请日：2019-12-12

Applicant: Silicon Laboratories Inc.

Inventor： Hendricus De Ruijter ,  Antonio Torrini ,  Yan Zhou ,  David Trager

IPC: H04B7/10 ,  H04B7/08 ,  H04B17/318

Abstract: In one embodiment, an apparatus includes: an antenna switch to receive a first radio frequency (RF) signal from a first antenna and a second RF signal from a second antenna and controllable to output a selected one of the first and second RF signals; an RF circuit to receive and process the first and second RF signals; at least one mixer to downconvert the first and second RF signals to first and second baseband signals; and an antenna diversity control circuit to receive sub-symbol portions of a first plurality of symbols of the first baseband signal and sub-symbol portions of a second plurality of symbols of the second baseband signal, and control the antenna switch to output one of the first and second RF signals, based at least in part on one or more of the sub-symbol portions of the first and second pluralities of symbols.

公开(公告)号：US10903838B1

公开(公告)日：2021-01-26

申请号：US16656867

申请日：2019-10-18

Applicant: Silicon Laboratories Inc.

Inventor： Brian Taylor Brunn ,  Paul Ivan Zavalney ,  Adrianus Josephus Bink ,  Chester Yu

IPC: G06F1/08 ,  G06F1/324 ,  H03K19/00

Abstract: An integrated circuit includes a clock management unit that selectively provides a clock signal, an energy management circuit that provides an internal power supply voltage to an internal voltage rail in response to an external power supply voltage, and has a capacitor coupled between the internal voltage rail and a reference voltage terminal, and a clocked digital circuit that is coupled to the internal voltage rail and the reference voltage terminal and operates in synchronism with the clock signal. The clock management unit provides the clock signal at a first frequency during a standby state, continuously at a second frequency higher than the first frequency during an active state, and during a first clock cycle following an end of the standby state while suppressing the clock signal during at least one subsequent clock cycle during a transition state between the standby state and the active state.

公开(公告)号：US10833400B2

公开(公告)日：2020-11-10

申请号：US16439458

申请日：2019-06-12

Applicant: Silicon Laboratories Inc.

Inventor： Pasi Rahikkala ,  Attila Zolomy

IPC: H01Q1/38 ,  H01Q1/24 ,  H01Q9/04 ,  H01Q9/14

Abstract: An apparatus includes a radio frequency (RF) circuit to transmit or receive RF signals, and a partitioned antenna structure. The partitioned antenna structure includes a first portion of a resonator and a first portion of a radiator. The first portion of the resonator comprises less than an entire resonator. The first portion of the radiator comprises less than an entire radiator.

公开(公告)号：US10826677B2

公开(公告)日：2020-11-03

申请号：US16546691

申请日：2019-08-21

Applicant: Silicon Laboratories Inc.

Inventor： Hua Beng Chan ,  Rex Wong Tak Ying ,  Ricky Setiawan ,  Obaida Mohammed Khaled Abu Hilal

IPC: H04L7/033

Abstract: In one aspect, an apparatus includes: a first time-to-data converter (TDC) to oversample a first duration of incoming data and hold the oversampled first duration during receipt of a second duration of the incoming data; a second TDC to oversample the second duration of the incoming data and hold the oversampled second duration during receipt of a third duration of the incoming data; a processing circuit coupled to the first and second TDCs, the processing circuit including a first filter to filter the oversampled first duration and the oversampled second duration and generate a control output therefrom; and a digitally controlled oscillator (DCO) coupled to the processing circuit to receive the control output and generate a recovery clock signal therefrom.

公开(公告)号：US10819353B1

公开(公告)日：2020-10-27

申请号：US16593473

申请日：2019-10-04

Applicant: Silicon Laboratories Inc.

Inventor： Timothy A. Monk ,  Douglas F. Pastorello

IPC: H03L7/08 ,  H03L7/087 ,  H03L7/22 ,  H03L7/23 ,  H03L7/093 ,  G01R31/317

Abstract: A spur target frequency is periodically determined to cancel a spur using a spur cancellation circuit in a first phase-locked loop (PLL) in a system with at least a second PLL that is in lock with the first PLL. The spur target frequency is periodically determined utilizing divide ratios of the first PLL and the second PLL to determine the updated spur target frequency. As one or more of the divide ratios change, the spur frequency changes and the spur target frequency is updated to reflect the change.