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公开(公告)号：US12175118B2
公开(公告)日：2024-12-24
申请号：US17700906
申请日：2022-03-22
Applicant: Silicon Laboratories Inc.
Inventor： Thomas Saroshan David , Aslam Rafi , Joshua Norem , Adrianus Josephus Bink , Daniel Cooley
IPC: G06F3/06
Abstract: An external nonvolatile memory device that includes a rewritable nonvolatile memory and a CMOS interface is disclosed. The interface includes a clock signal which is input to the external nonvolatile memory device. This clock signal is multiplied by an integer to create a memory serdes clock which is used to clock outgoing data. The memory serdes clock is also used to create a clock that is used to clock the incoming data from the main processing device. The external nonvolatile memory device also includes an encryption/decryption block that encrypts data read from the nonvolatile memory before it is transmitted over the interface, and decrypts data received from the interface before storing it in the nonvolatile memory. The encryption/decryption block may utilize a stream cipher.
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公开(公告)号：US20210080993A1
公开(公告)日：2021-03-18
申请号：US16569991
申请日：2019-09-13
Applicant: Silicon Laboratories Inc.
Inventor： Thomas Saroshan David
IPC: G06F1/08 , H03K17/687
Abstract: A configurable clock buffer including first and second buffers and isolation circuitry. The first buffer has an input coupled to a clock input node and has an output coupled to a clock output node. The second buffer has an input coupled to an intermediate input node and has an output coupled to an intermediate output node. The isolation circuitry is responsive to at least one mode signal, in which it electrically couples the intermediate input node to the clock input node and electrically couples the intermediate output node to the clock output node when the at least one mode signal is in a first state, and in which it electrically couples the intermediate input node to a static node and electrically isolates the intermediate output node from the clock output node when the at least one mode signal is in a second state.
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3.发明申请公开(公告)号：US20150269106A1
公开(公告)日：2015-09-24
申请号：US14224057
申请日：2014-03-24
Applicant: Silicon Laboratories Inc.
Inventor： Kenneth W. Fernald , Phillip Matthews , Thomas Saroshan David
CPC classification number: G06F13/423 , G06F1/3203 , G06F11/30 , G06F11/3048 , G06F13/385 , Y02B70/12 , Y02B70/123 , Y02D10/14 , Y02D10/151
Abstract: A system for communicating information includes one device that communicates information via a communication link. The system also includes a second device to communicate information via the communication link. The second device includes a receiver to receive information from the communication link. The second device also includes an oscillator that provides at least one timing signal to the receiver. The oscillator is disabled when the communication link is in an idle state. The oscillator is enabled when the communication link is in a non-idle state.
Abstract translation: 用于传送信息的系统包括经由通信链路传送信息的一个设备。 该系统还包括通过通信链路传送信息的第二设备。 第二设备包括从通信链路接收信息的接收器。 第二装置还包括向接收器提供至少一个定时信号的振荡器。 当通信链路处于空闲状态时，振荡器被禁止。 当通信链路处于非空闲状态时，振荡器被使能。
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公开(公告)号：US11106235B2
公开(公告)日：2021-08-31
申请号：US16569991
申请日：2019-09-13
Applicant: Silicon Laboratories Inc.
Inventor： Thomas Saroshan David
IPC: G06F1/08 , H03K17/687
Abstract: A configurable clock buffer including first and second buffers and isolation circuitry. The first buffer has an input coupled to a clock input node and has an output coupled to a clock output node. The second buffer has an input coupled to an intermediate input node and has an output coupled to an intermediate output node. The isolation circuitry is responsive to at least one mode signal, in which it electrically couples the intermediate input node to the clock input node and electrically couples the intermediate output node to the clock output node when the at least one mode signal is in a first state, and in which it electrically couples the intermediate input node to a static node and electrically isolates the intermediate output node from the clock output node when the at least one mode signal is in a second state.
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公开(公告)号：US20150271756A1
公开(公告)日：2015-09-24
申请号：US14224048
申请日：2014-03-24
Applicant: Silicon Laboratories Inc.
Inventor： Kenneth W. Fernald , Phillip Matthews , Thomas Saroshan David
IPC: H04W52/02
CPC classification number: H04W52/0241 , H04W52/0222 , H04W52/0251 , Y02D70/00
Abstract: An apparatus includes a detector to detect an idle state of a communication link that communicates bursts or packets of information. The apparatus also includes an oscillator having low-power and normal modes of operation. The oscillator makes a transition to the low-power mode during the idle state of the communication link. The oscillator leaves the low-power mode of operation and enters the normal mode of operation when the communication link is in a non-idle state.
Abstract translation: 一种装置包括检测器，用于检测通信链路的空闲状态，所述通信链路传送脉冲串或信息包。 该装置还包括具有低功率和正常工作模式的振荡器。 在通信链路的空闲状态期间，振荡器转换到低功率模式。 当通信链路处于非空闲状态时，振荡器离开低功耗操作模式并进入正常工作模式。
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Patent Agency Ranking
公开(公告)号：US20150235606A1
公开(公告)日：2015-08-20
申请号：US14571248
申请日：2014-12-15
Applicant: Silicon Laboratories Inc.
Inventor： Douglas Piasecki , Thomas Saroshan David , Timothy T. Rueger , Stefan Mastovich , Jia-Hau Liu
CPC classification number: G09G3/3696 , G06F3/0412 , G06F3/044 , G09G3/18 , G09G3/3611 , G09G5/18 , G09G2310/0278 , G09G2330/02 , G09G2330/021 , G09G2330/022
Abstract: An LCD controller includes a charge pump circuit for generating a charge voltage responsive to an external voltage and a clock signal. An oscillator generates the clock signal responsive to at least one bias voltage. The oscillator has a high power mode of operation and a low power mode of operation. Bias circuitry for applies the at least one bias voltage to the oscillator. The at least one bias voltage is applied to the oscillator from an external source in the high power mode of operation and the at least one bias voltage is applied to the oscillator from a source within the oscillator in the low power mode of operation. An LCD driver voltage circuit generates a plurality of LCD driver voltages for driving segments of an LCD display responsive to the charge voltage.
Abstract translation: LCD控制器包括用于产生响应于外部电压和时钟信号的充电电压的电荷泵电路。 振荡器响应于至少一个偏置电压产生时钟信号。 振荡器具有高功率工作模式和低功耗工作模式。 用于将至少一个偏置电压施加到振荡器的偏置电路。 在高功率工作模式下，至少一个偏置电压从外部源施加到振荡器，并且至少一个偏置电压在低功耗工作模式下从振荡器内的源施加到振荡器。 LCD驱动器电压电路响应于充电电压产生用于驱动LCD显示器段的多个LCD驱动器电压。
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公开(公告)号：US11768794B1
公开(公告)日：2023-09-26
申请号：US17700907
申请日：2022-03-22
Applicant: Silicon Laboratories Inc.
Inventor： Aslam Rafi , Thomas Saroshan David , Daniel Cooley
CPC classification number: G06F13/4068 , G06F1/12
Abstract: An interface between two devices is disclosed. To consume power, the signals used in the interface utilize CMOS signalling. Further, to achieve high speed, a reduced frequency clock is transmitted from one device to the second device. The second device has a clock multiplier to recreate the original clock. Both devices utilize a clock phase alignment block which aligns the phase of the clock with the incoming data. The clock phase alignment block utilizes a digital PLL to consume power. Further, since the digital PLL retains its state, the reduced frequency clock may be disabled when data is not being transmitted. This interface may be used to transmit serial data at rates up to and exceeding 2.5 Gbits/sec.
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8.发明授权公开(公告)号：US11374600B1
公开(公告)日：2022-06-28
申请号：US17160835
申请日：2021-01-28
Applicant: Silicon Laboratories Inc.
Inventor： Thomas Saroshan David , Michael Johnson , Paul Zavalney
Abstract: In one example, an apparatus includes: a radio frequency (RF) receiver to receive an RF signal; a media access control (MAC) circuit to receive data and output MAC-processed data according to a clock signal that is phase delayed with respect to a source clock signal when the RF receiver is active; and an interference mitigation circuit to receive the MAC-processed data and provide the MAC-processed data to a physical circuit resynchronized to the source clock signal.
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公开(公告)号：US10514747B2
公开(公告)日：2019-12-24
申请号：US14869926
申请日：2015-09-29
Applicant: Silicon Laboratories Inc.
Inventor： Kenneth W. Fernald , Thomas Saroshan David
IPC: G06F1/3234 , G06F1/3206 , H04W52/02
Abstract: An apparatus includes a communication circuit coupled to a communication link, a wakeup detector, and a power control circuit. The communication circuit has a first state and a second state. The power consumption of the communication circuit is lower in the second state than in the first state. The wakeup detector is coupled to the communication link. The wakeup detector generates a wakeup signal to cause the communication circuit to make a transition from the second state to the first state in response to an occurrence of an event on the communication link. The power control circuit selectively supplies power to the communication circuit in response to the wakeup signal.
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公开(公告)号：US09612893B2
公开(公告)日：2017-04-04
申请号：US14709204
申请日：2015-05-11
Applicant: Silicon Laboratories Inc.
Inventor： Thomas Saroshan David
CPC classification number: G06F11/0757 , G06F11/00 , G06F11/0706
Abstract: In some embodiments, a circuit may include a plurality of peripherals and a peripheral watchdog timer circuit coupled to at least one of the plurality of peripherals. The peripheral watchdog timer circuit may be configured to count clock cycles and concurrently to detect activity associated with at least one of the plurality of peripherals. The peripheral watchdog timer circuit may be configured to reset a count in response to detecting the activity. In some embodiments, the peripheral watchdog timer circuit may be configured to generate an alert signal when the count exceeds a threshold count before detecting the activity. In some embodiments, the peripheral watchdog timer circuit is configured to initiate a reset operation when the alert is not serviced within a period of time.
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