公开(公告)号：US20230305737A1

公开(公告)日：2023-09-28

申请号：US17700906

申请日：2022-03-22

Applicant: Silicon Laboratories Inc.

Inventor： Thomas Saroshan David ,  Aslam Rafi ,  Joshua Norem ,  Adrianus Josephus Bink ,  Daniel Cooley

IPC: G06F3/06

CPC classification number: G06F3/0655 ,  G06F3/0613 ,  G06F3/0622 ,  G06F3/0679

Abstract: An external nonvolatile memory device that includes a rewritable nonvolatile memory and a CMOS interface is disclosed. The interface includes a clock signal which is input to the external nonvolatile memory device. This clock signal is multiplied by an integer to create a memory serdes clock which is used to clock outgoing data. The memory serdes clock is also used to create a clock that is used to clock the incoming data from the main processing device. The external nonvolatile memory device also includes an encryption/decryption block that encrypts data read from the nonvolatile memory before it is transmitted over the interface, and decrypts data received from the interface before storing it in the nonvolatile memory. The encryption/decryption block may utilize a stream cipher.

公开(公告)号：US12175118B2

公开(公告)日：2024-12-24

申请号：US17700906

申请日：2022-03-22

Applicant: Silicon Laboratories Inc.

Inventor： Thomas Saroshan David ,  Aslam Rafi ,  Joshua Norem ,  Adrianus Josephus Bink ,  Daniel Cooley

IPC: G06F3/06

Abstract: An external nonvolatile memory device that includes a rewritable nonvolatile memory and a CMOS interface is disclosed. The interface includes a clock signal which is input to the external nonvolatile memory device. This clock signal is multiplied by an integer to create a memory serdes clock which is used to clock outgoing data. The memory serdes clock is also used to create a clock that is used to clock the incoming data from the main processing device. The external nonvolatile memory device also includes an encryption/decryption block that encrypts data read from the nonvolatile memory before it is transmitted over the interface, and decrypts data received from the interface before storing it in the nonvolatile memory. The encryption/decryption block may utilize a stream cipher.

公开(公告)号：US10903838B1

公开(公告)日：2021-01-26

申请号：US16656867

申请日：2019-10-18

Applicant: Silicon Laboratories Inc.

Inventor： Brian Taylor Brunn ,  Paul Ivan Zavalney ,  Adrianus Josephus Bink ,  Chester Yu

IPC: G06F1/08 ,  G06F1/324 ,  H03K19/00

Abstract: An integrated circuit includes a clock management unit that selectively provides a clock signal, an energy management circuit that provides an internal power supply voltage to an internal voltage rail in response to an external power supply voltage, and has a capacitor coupled between the internal voltage rail and a reference voltage terminal, and a clocked digital circuit that is coupled to the internal voltage rail and the reference voltage terminal and operates in synchronism with the clock signal. The clock management unit provides the clock signal at a first frequency during a standby state, continuously at a second frequency higher than the first frequency during an active state, and during a first clock cycle following an end of the standby state while suppressing the clock signal during at least one subsequent clock cycle during a transition state between the standby state and the active state.