Abstract:
PROBLEM TO BE SOLVED: To provide a method for forming base and emitter regions in a bipolar transistor. SOLUTION: This method includes the steps of forming a first heavily-doped P-type polysilicon layer 6 through deposition, removing the central part of the first polysilicon layer 6, forming a thermal oxidation film 8 on the removed part by growing, subjecting the layer 8 to a P-type implantation 30 with use of a first dose, forming a silicon nitride spacer 15 in an inner periphery of the first polysilicon layer, subjecting the layer 8 to a second P-type implantation 31 with use of a second dose, removing the central oxide layer 8, forming a second N-type polysilicon layer 18 through deposition, and performing high-speed thermal annealing treatment thereover and the second dose is selected so as to optimize the base-emitter junction characteristic, and the first dose is set smaller than the second dose.
Abstract:
PROBLEM TO BE SOLVED: To deposit silicon at a low temperature, by deciding a window on a single crystal silicon substrate, and generating an inter-lattice defect in terms of atoms at a specified rate in the window. SOLUTION: A window 13 is given on a single crystal silicon substrate 11. The surface of the area of a layer which is not covered by the window is processed in a way that a lattice defect is generated at the rate of one percent in terms of atoms to the depth of below 5 μm in a crystal lattice in a region 14 which is not covered. When the stage of any annealing is not executed immediately after the processing, an upper layer 15 is processed with conditions that a state is that of pressure reduction at the temperature below that at which epitaxial deposition is generally executed, a range is 600-700°C and below 900°C, reaction gas is silane (SiH 4 ) and pressure reduction is about 0.1×10 5 Pa (80 Torr). The layer 15 is similar to the substrate 11 but it has single crystal structure following a crystal axis different form the crystal axis of the substrate 11. COPYRIGHT: (C)1999,JPO
Abstract:
PROBLEM TO BE SOLVED: To eliminate the polishing of a conductive material and form a damascene type wiring and a contact in an integrated circuit by depositing a first dielectric layer on an upper plane of a lower layer, forming a cavity that extends through the part of the first dielectric layer at a position selected for forming a conductive part and by filling the cavity with the conductive material. SOLUTION: A semiconductor substrate 10 includes a contact region 12, which corresponds to the substrate doped region of a transistor source or a drain in a MOS integrated circuit at a position selected for forming a contact, etc. The contact region is electrically brought into contact with or isolated from the substrate 10, and can be substituted with other conductive layers such as polysilicon and silicide layers. A first dielectric layer 14 is deposited over the entire upper plane of the structure (substrate). In the case where a second conductive layer 22 constitutes an interface with the contact region 12, resistance is made relatively low. A contact 30 having a recess is formed by a damascene process through a dielectric layer 14.
Abstract:
PROBLEM TO BE SOLVED: To enable a microprobe to be easily and automatically adjusted at a contact point by a method, wherein the contact point formed on the surface of a board and a guide means used for a test probe which moves on the surface of the board toward the contact point are provided. SOLUTION: A test region incorporated in a board is equipped with a nearly circular center contact point 14 formed of the surface of a metal small disk. The contact point 14 is surrounded by eight long and thin rectangular guide means (bosses) 16. The bosses 16 are arranged adjacent to the contact point 14 and directed to the center of the contact point 14 in the radial directions. The edges 16a of the bosses 16 which are directed toward the contact point 14 are arranged adequately separately from each other to give passages for a microprobe 20 to move on the surface of the board. Moreover, the edge of the microprobe 20 is connected electrically to the contact point 14.
Abstract:
PROBLEM TO BE SOLVED: To obtain a coil which emits a low electric field by forming a conductive screen substantially in the same shape as a winding and forming an open loop circuit having a shield zone. SOLUTION: The coil 30 has a metal screen 35, coupled fixedly with a plate 33, on its reverse surface 30-2. The screen 35 is in the same shape as the winding 31 and its position on the reverse surface 30-2 is aligned with the position of the winding 31 on the front 30-1. The screen 35 is shaped in a frame having external dimensions L1 and I1 and internal dimensions L2 and I2 . Further, the screen 35 has the shield zone 36 and therefore forms the open loop conductive circuit including two ends 37 and 38 which never meet each other. The screen 35 never disturbs an effective magnetic field B which is directed along the axis and makes ineffective a parasitic electric field radiated by the winding 31. Consequently, a main feature which can be obtained is the shield zone and in the absence of this, the screen 35 forms the open loop circuit to short-circuit the magnetic field B.
Abstract:
PROBLEM TO BE SOLVED: To provide a small-size memory point by a CMOS technology, by modifying gate-well resistance by means of current flowing from the drain and the source to a well, and programming a memory point depending on the state of the gate in the programming stage. SOLUTION: During programming, a well 1 of a MOS transistor is connected to the reference potential. The drain 5 and the source 4 are connected to a source of current so that a space charge region may be expanded along the entire length of the channel, and the drain 5 and the source 4 may be biased so that an avalenche may appear in the opposite direction to the junction between the drain 5 and the source 4. The gate 6 is set to the reference potential when a memory point needs not to be programmed while set to the other potential when the memory point needs to be programmed. Furthermore, a means for detecting whether the impedance between the gate 6 and the well 1 is high or low during reading is installed.
Abstract:
PROBLEM TO BE SOLVED: To provide a variable gain amplifier capable of reducing device current consumption and area by extremely decreasing the number of components through which RF signal must pass. SOLUTION: The variable gain amplifier comprises: an input node; a variable current source coupled to the input node; first and second branches coupled in parallel between a first supply terminal and the variable current source, the first and second branches defining a differential pair arranged to be controlled by first and second differential gain signals and having first and second output terminals, one of the output terminals including an output node of the variable gain amplifier; and a potential divider having a middle node coupled to the first and second output terminals, wherein the middle node is also coupled to the input node via a capacitor. COPYRIGHT: (C)2010,JPO&INPIT
Abstract:
PROBLEM TO BE SOLVED: To form a structure of a component for attaining function of a photo-sensor and a dimmer while saving its space. SOLUTION: A light control detection MOSFET has two source and drain regions separated with a channel 130 extending along a first direction, and a substrate 100 irradiated with light and a gate conductive beam 140 extending along a second direction which is almost perpendicular to the first direction. On at least one supporting region, the beam is fixed at each of two edge portions and located on the channel region 130. The gate beam is almost opaque and flexible so that progressive modulation is applied to light reaching the channel 130 based on a curve which is controlled by a voltage difference between a gate voltage and bulk voltage wherein the voltage difference acts so as to bend the beam to come closer to the channel surface. COPYRIGHT: (C)2009,JPO&INPIT
Abstract:
PROBLEM TO BE SOLVED: To provide a manufacturing method for a transistor with a germanium-rich channel and fully-depleted type architecture that can be easily manufactured on an arbitrary substrate and that can easily control the formation of the channel. SOLUTION: The manufacturing method for a MOS transistor comprises (a) a step to form a half-conductive interlayer 6 containing alloy of silicon and germanium on a substrate 2, (b) step to manufacture the source region, drain region and insulating gate regions 11, 12 and 9 of the transistor on the interlayer 6, and (c) step to oxidize the interlayer 6 starting with the bottom surface of the interlayer 6 to raise the concentration of germanium within the channel of the transistor. COPYRIGHT: (C)2008,JPO&INPIT
Abstract:
PROBLEM TO BE SOLVED: To provide an easy method for forming a compact pad whose manufacturing cost can be reduced. SOLUTION: A region 51 is an area 510 that extends at least up to part of the front surface of the region, and can be locally changed for the purpose of forming the area using a material that can be selectively removed from the region. This region is covered with an insulating material 7, and an orifice 90 that appears on the front surface of the area 510 is formed in the insulating material. The material that can be selectively removed is removed from this area through the orifice so that a cavity 520 may be formed in place of this area. The cavity and the orifice are filled up with at least one conductive material 91. COPYRIGHT: (C)2006,JPO&NCIPI