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    BASE AND EMITTER REGIONS FOR SUBMICRON BIPOLAR TRANSISTOR
    131.
    发明专利
    BASE AND EMITTER REGIONS FOR SUBMICRON BIPOLAR TRANSISTOR 失效

    公开(公告)号：JPH11340245A

    公开(公告)日：1999-12-10

    申请号：JP8607199

    申请日：1999-03-29

    Applicant: ST MICROELECTRONICS SA

    Inventor： GRIS YVON

    IPC: H01L29/73 ,  H01L21/265 ,  H01L21/331 ,  H01L21/8249 ,  H01L29/10 ,  H01L29/732

    Abstract: PROBLEM TO BE SOLVED: To provide a method for forming base and emitter regions in a bipolar transistor. SOLUTION: This method includes the steps of forming a first heavily-doped P-type polysilicon layer 6 through deposition, removing the central part of the first polysilicon layer 6, forming a thermal oxidation film 8 on the removed part by growing, subjecting the layer 8 to a P-type implantation 30 with use of a first dose, forming a silicon nitride spacer 15 in an inner periphery of the first polysilicon layer, subjecting the layer 8 to a second P-type implantation 31 with use of a second dose, removing the central oxide layer 8, forming a second N-type polysilicon layer 18 through deposition, and performing high-speed thermal annealing treatment thereover and the second dose is selected so as to optimize the base-emitter junction characteristic, and the first dose is set smaller than the second dose.

    Method for depositing single crystal silicon region
    132.
    发明专利
    Method for depositing single crystal silicon region 审中-公开
    沉积单晶硅区域的方法

    公开(公告)号：JPH11274171A

    公开(公告)日：1999-10-08

    申请号：JP1441499

    申请日：1999-01-22

    Applicant: St Microelectronics Sa ,  エステーミクロエレクトロニクス ソシエテ アノニム

    Inventor： GRIS YVON ,  TROILLARD GERMAINE ,  MOURIER JOCELYNE

    IPC: H01L29/73 ,  C30B25/02 ,  H01L21/20 ,  H01L21/205 ,  H01L21/331 ,  H01L29/732

    CPC classification number: C30B29/06 ,  C30B25/02 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/0262 ,  H01L29/66287 ,  Y10S117/913

    Abstract: PROBLEM TO BE SOLVED: To deposit silicon at a low temperature, by deciding a window on a single crystal silicon substrate, and generating an inter-lattice defect in terms of atoms at a specified rate in the window.
    SOLUTION: A window 13 is given on a single crystal silicon substrate 11. The surface of the area of a layer which is not covered by the window is processed in a way that a lattice defect is generated at the rate of one percent in terms of atoms to the depth of below 5 μm in a crystal lattice in a region 14 which is not covered. When the stage of any annealing is not executed immediately after the processing, an upper layer 15 is processed with conditions that a state is that of pressure reduction at the temperature below that at which epitaxial deposition is generally executed, a range is 600-700°C and below 900°C, reaction gas is silane (SiH
    4 ) and pressure reduction is about 0.1×10
    5 Pa (80 Torr). The layer 15 is similar to the substrate 11 but it has single crystal structure following a crystal axis different form the crystal axis of the substrate 11.
    COPYRIGHT: (C)1999,JPO

    Abstract translation: 要解决的问题：通过在单晶硅衬底上确定窗口并在窗口中以规定的速率产生晶格间缺陷，以便在低温下沉积硅。 解决方案：在单晶硅衬底11上提供窗口13.未被窗口覆盖的层的区域的表面以如下方式进行处理，即以1％的速率产生晶格缺陷， 原子在未被覆盖的区域14中的晶格中的5μm以下的深度。 当在处理之后立即执行任何退火阶段时，上层15的处理条件是在低于通常执行外延沉积的温度下的压力降低的状态，范围为600-700度 ℃，900℃以下，反应气体为硅烷（SiH4），减压约为0.1×10 5 Pa（80托）。 层15与基板11相似，但是具有与基板11的晶轴不同的晶轴的单晶结构。

    METHOD FOR FORMING CONDUCTIVE PART IN INTEGRATED CIRCUIT
    133.
    发明专利
    METHOD FOR FORMING CONDUCTIVE PART IN INTEGRATED CIRCUIT 失效

    公开(公告)号：JPH11251436A

    公开(公告)日：1999-09-17

    申请号：JP37016698

    申请日：1998-12-25

    Applicant: ST MICROELECTRONICS SA ,  COMMISSARIAT ENERGIE ATOMIQUE

    Inventor： MOUSSAVI MEHDI ,  MORAND YVES

    IPC: H01L21/288 ,  H01L21/768

    Abstract: PROBLEM TO BE SOLVED: To eliminate the polishing of a conductive material and form a damascene type wiring and a contact in an integrated circuit by depositing a first dielectric layer on an upper plane of a lower layer, forming a cavity that extends through the part of the first dielectric layer at a position selected for forming a conductive part and by filling the cavity with the conductive material. SOLUTION: A semiconductor substrate 10 includes a contact region 12, which corresponds to the substrate doped region of a transistor source or a drain in a MOS integrated circuit at a position selected for forming a contact, etc. The contact region is electrically brought into contact with or isolated from the substrate 10, and can be substituted with other conductive layers such as polysilicon and silicide layers. A first dielectric layer 14 is deposited over the entire upper plane of the structure (substrate). In the case where a second conductive layer 22 constitutes an interface with the contact region 12, resistance is made relatively low. A contact 30 having a recess is formed by a damascene process through a dielectric layer 14.

    TESTING REGION FOR AUTOMATIC POSITIONING OF MICROPROBE AND MANUFACTURE THEREOF
    134.
    发明专利
    TESTING REGION FOR AUTOMATIC POSITIONING OF MICROPROBE AND MANUFACTURE THEREOF 失效

    公开(公告)号：JPH11243121A

    公开(公告)日：1999-09-07

    申请号：JP30020898

    申请日：1998-10-21

    Applicant: ST MICROELECTRONICS SA

    Inventor： VALLET MICHEL

    IPC: G01R1/06 ,  G01R31/28 ,  H01L21/66 ,  H01L21/822 ,  H01L27/04

    Abstract: PROBLEM TO BE SOLVED: To enable a microprobe to be easily and automatically adjusted at a contact point by a method, wherein the contact point formed on the surface of a board and a guide means used for a test probe which moves on the surface of the board toward the contact point are provided. SOLUTION: A test region incorporated in a board is equipped with a nearly circular center contact point 14 formed of the surface of a metal small disk. The contact point 14 is surrounded by eight long and thin rectangular guide means (bosses) 16. The bosses 16 are arranged adjacent to the contact point 14 and directed to the center of the contact point 14 in the radial directions. The edges 16a of the bosses 16 which are directed toward the contact point 14 are arranged adequately separately from each other to give passages for a microprobe 20 to move on the surface of the board. Moreover, the edge of the microprobe 20 is connected electrically to the contact point 14.

    ANTENNA COIL ACCOMPANIED BY REDUCED ELECTRIC FIELD
    135.
    发明专利
    ANTENNA COIL ACCOMPANIED BY REDUCED ELECTRIC FIELD 失效

    公开(公告)号：JPH11239016A

    公开(公告)日：1999-08-31

    申请号：JP34363398

    申请日：1998-11-18

    Applicant: ST MICROELECTRONICS SA

    Inventor： ENGUENT JEAN-PIERRE

    IPC: H01Q1/38 ,  G06K7/08 ,  G06K19/077 ,  H01Q7/00

    Abstract: PROBLEM TO BE SOLVED: To obtain a coil which emits a low electric field by forming a conductive screen substantially in the same shape as a winding and forming an open loop circuit having a shield zone. SOLUTION: The coil 30 has a metal screen 35, coupled fixedly with a plate 33, on its reverse surface 30-2. The screen 35 is in the same shape as the winding 31 and its position on the reverse surface 30-2 is aligned with the position of the winding 31 on the front 30-1. The screen 35 is shaped in a frame having external dimensions L1 and I1 and internal dimensions L2 and I2 . Further, the screen 35 has the shield zone 36 and therefore forms the open loop conductive circuit including two ends 37 and 38 which never meet each other. The screen 35 never disturbs an effective magnetic field B which is directed along the axis and makes ineffective a parasitic electric field radiated by the winding 31. Consequently, a main feature which can be obtained is the shield zone and in the absence of this, the screen 35 forms the open loop circuit to short-circuit the magnetic field B.

    MOS MEMORY POINT
    136.
    发明专利
    MOS MEMORY POINT 失效

    公开(公告)号：JPH11214538A

    公开(公告)日：1999-08-06

    申请号：JP31533398

    申请日：1998-10-20

    Applicant: ST MICROELECTRONICS SA

    Inventor： PAPADAS CONSTANTIN ,  SCHOELLKOPF JEAN-PIERRE

    IPC: H01L27/112 ,  G11C17/16 ,  H01L21/8246

    Abstract: PROBLEM TO BE SOLVED: To provide a small-size memory point by a CMOS technology, by modifying gate-well resistance by means of current flowing from the drain and the source to a well, and programming a memory point depending on the state of the gate in the programming stage. SOLUTION: During programming, a well 1 of a MOS transistor is connected to the reference potential. The drain 5 and the source 4 are connected to a source of current so that a space charge region may be expanded along the entire length of the channel, and the drain 5 and the source 4 may be biased so that an avalenche may appear in the opposite direction to the junction between the drain 5 and the source 4. The gate 6 is set to the reference potential when a memory point needs not to be programmed while set to the other potential when the memory point needs to be programmed. Furthermore, a means for detecting whether the impedance between the gate 6 and the well 1 is high or low during reading is installed.

    Variable gain rf amplifier
    137.
    发明专利
    Variable gain rf amplifier 有权
    可变增益射频放大器

    公开(公告)号：JP2009260972A

    公开(公告)日：2009-11-05

    申请号：JP2009102195

    申请日：2009-04-20

    Applicant: St Microelectronics Sa ,  エス テ マイクロエレクトロニクス エス アー

    Inventor： TOUZARD OLIVIER ,  TOURNIER VERONIQUE

    IPC: H03G3/10 ,  H03F3/45

    CPC classification number: H03G1/0023 ,  H03F3/19 ,  H03F3/45089 ,  H03F2200/294 ,  H03F2203/45392

    Abstract: PROBLEM TO BE SOLVED: To provide a variable gain amplifier capable of reducing device current consumption and area by extremely decreasing the number of components through which RF signal must pass. SOLUTION: The variable gain amplifier comprises: an input node; a variable current source coupled to the input node; first and second branches coupled in parallel between a first supply terminal and the variable current source, the first and second branches defining a differential pair arranged to be controlled by first and second differential gain signals and having first and second output terminals, one of the output terminals including an output node of the variable gain amplifier; and a potential divider having a middle node coupled to the first and second output terminals, wherein the middle node is also coupled to the input node via a capacitor. COPYRIGHT: (C)2010,JPO&INPIT

    Abstract translation: 要解决的问题：提供一种可以通过极大地减少RF信号必须通过的分量的数量来减少器件电流消耗和面积的可变增益放大器。 解决方案：可变增益放大器包括：输入节点; 耦合到所述输入节点的可变电流源; 第一和第二分支并联耦合在第一电源端子和可变电流源之间，第一和第二分支限定一个差分对，其布置为由第一和第二差分增益信号控制，并具有第一和第二输出端子，输出之一 端子，包括可变增益放大器的输出节点; 以及具有耦合到所述第一和第二输出端子的中间节点的分压器，其中所述中间节点还经由电容器耦合到所述输入节点。 版权所有（C）2010，JPO＆INPIT

    Dimming detection mosfet, and manufacturing method thereof
    138.
    发明专利
    Dimming detection mosfet, and manufacturing method thereof 审中-公开
    调光检测MOSFET及其制造方法

    公开(公告)号：JP2009044127A

    公开(公告)日：2009-02-26

    申请号：JP2008120484

    申请日：2008-05-02

    Applicant: St Microelectronics Sa ,  エスティ マイクロエレクトロニクス エス.エイ.ST Microelectronics S.A.

    Inventor： ABELE NICOLAS

    IPC: H01L31/10 ,  H01L21/28 ,  H01L21/3205 ,  H01L23/52 ,  H01L29/417 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78 ,  H01L29/786

    CPC classification number: H01L31/1136 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: PROBLEM TO BE SOLVED: To form a structure of a component for attaining function of a photo-sensor and a dimmer while saving its space.
    SOLUTION: A light control detection MOSFET has two source and drain regions separated with a channel 130 extending along a first direction, and a substrate 100 irradiated with light and a gate conductive beam 140 extending along a second direction which is almost perpendicular to the first direction. On at least one supporting region, the beam is fixed at each of two edge portions and located on the channel region 130. The gate beam is almost opaque and flexible so that progressive modulation is applied to light reaching the channel 130 based on a curve which is controlled by a voltage difference between a gate voltage and bulk voltage wherein the voltage difference acts so as to bend the beam to come closer to the channel surface.
    COPYRIGHT: (C)2009,JPO&INPIT

    Abstract translation: 要解决的问题：为了形成用于获得光传感器和调光器的功能的部件的结构，同时节省空间。 光控制检测MOSFET具有沿着第一方向延伸的通道130和由光照射的基板100和沿第二方向延伸的栅极导电梁140分开的两个源极和漏极区域，第二方向几乎垂直于 第一个方向。 在至少一个支撑区域上，光束固定在两个边缘部分中的每一个并且位于通道区域130上。栅极光束几乎是不透明和柔性的，使得逐渐调制被施加到基于如下曲线的到达通道130的光 由栅极电压和体电压之间的电压差控制，其中电压差用于使光束弯曲成靠近通道表面。 版权所有（C）2009，JPO＆INPIT

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