公开(公告)号：JPH11224910A

公开(公告)日：1999-08-17

申请号：JP32135798

申请日：1998-10-28

Applicant: ST MICROELECTRONICS SA

Inventor： PAPADAS CONSTANTIN

IPC: G11C16/04 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/51 ,  H01L29/788 ,  H01L29/792

Abstract: PROBLEM TO BE SOLVED: To provide a new type of memory device having a simple structure that enables long-term residing using MOS technology. SOLUTION: This remaining, electrically programmable and erasable memory device has a MOS transistor containing a gate insulator of a charge transfer type. The gate insulator is provided with a laminate in the cross direction that comprises at least 5 regions, including the middle regions 14 and 15 having the first band gap value, with farthest end regions 11 and 12 having a band gap value larger than a first value, and the central region 13.

公开(公告)号：JPH11214538A

公开(公告)日：1999-08-06

申请号：JP31533398

申请日：1998-10-20

Applicant: ST MICROELECTRONICS SA

Inventor： PAPADAS CONSTANTIN ,  SCHOELLKOPF JEAN-PIERRE

IPC: H01L27/112 ,  G11C17/16 ,  H01L21/8246

Abstract: PROBLEM TO BE SOLVED: To provide a small-size memory point by a CMOS technology, by modifying gate-well resistance by means of current flowing from the drain and the source to a well, and programming a memory point depending on the state of the gate in the programming stage. SOLUTION: During programming, a well 1 of a MOS transistor is connected to the reference potential. The drain 5 and the source 4 are connected to a source of current so that a space charge region may be expanded along the entire length of the channel, and the drain 5 and the source 4 may be biased so that an avalenche may appear in the opposite direction to the junction between the drain 5 and the source 4. The gate 6 is set to the reference potential when a memory point needs not to be programmed while set to the other potential when the memory point needs to be programmed. Furthermore, a means for detecting whether the impedance between the gate 6 and the well 1 is high or low during reading is installed.

公开(公告)号：DE69615449T2

公开(公告)日：2002-06-13

申请号：DE69615449

申请日：1996-05-15

Applicant: ST MICROELECTRONICS SA

Inventor： PAPADAS CONSTANTIN ,  NIKOLAIDIS THEODOROS

IPC: H01L27/04 ,  H01L21/822 ,  H01L21/8234 ,  H01L27/02 ,  H01L27/088 ,  H01L29/78

公开(公告)号：DE69509581D1

公开(公告)日：1999-06-17

申请号：DE69509581

申请日：1995-03-24

Applicant: ST MICROELECTRONICS SA

Inventor： PAPADAS CONSTANTIN ,  GUILLAUMOT BERNARD

IPC: H01L21/8247 ,  G11C11/56 ,  H01L21/28 ,  H01L21/336 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792 ,  G11C16/06 ,  G11C16/04

Abstract: The memory cell comprises a p-type channel and gate between an n-type source (12) layer and drain (13) layer with an inner extension (14,15) of lightly doped n-type layer into the gate region. The main isolated gate (GC) is situated over the gate region and the floating gate (GF) is situated over the lightly doped drain region. In charging the cell excess electrons pass to the extension zone and the floating command.

公开(公告)号：DE69825646T2

公开(公告)日：2005-08-18

申请号：DE69825646

申请日：1998-02-24

Applicant: ST MICROELECTRONICS SA

Inventor： BOURAS ILIAS ,  PAPADAS CONSTANTIN ,  MOREAU JEAN-PIERRE

IPC: G06F3/00 ,  H03K19/017 ,  H03K19/0175 ,  H03K19/0185

Abstract: The amplifier an input wire (E) which passes signals to two MOS transistors (N3,N4) in parallel. The centre point (10) of the transistors drives an output transistor (N2) driving an output line (S). The two parallel transistors set a low level directed by an input signal, and a high level commanded by the input signal respectively. The high level setting transistor has a drain junction with a very abrupt characteristic providing fast switching.

公开(公告)号：DE69825646D1

公开(公告)日：2004-09-23

申请号：DE69825646

申请日：1998-02-24

Applicant: ST MICROELECTRONICS SA

Inventor： BOURAS ILIAS ,  PAPADAS CONSTANTIN ,  MOREAU JEAN-PIERRE

IPC: G06F3/00 ,  H03K19/017 ,  H03K19/0175 ,  H03K19/0185

Abstract: The amplifier an input wire (E) which passes signals to two MOS transistors (N3,N4) in parallel. The centre point (10) of the transistors drives an output transistor (N2) driving an output line (S). The two parallel transistors set a low level directed by an input signal, and a high level commanded by the input signal respectively. The high level setting transistor has a drain junction with a very abrupt characteristic providing fast switching.

公开(公告)号：DE69509581T2

公开(公告)日：1999-12-23

申请号：DE69509581

申请日：1995-03-24

Applicant: ST MICROELECTRONICS SA

Inventor： PAPADAS CONSTANTIN ,  GUILLAUMOT BERNARD

IPC: H01L21/8247 ,  G11C11/56 ,  H01L21/28 ,  H01L21/336 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792 ,  G11C16/06 ,  G11C16/04

Abstract: The memory cell comprises a p-type channel and gate between an n-type source (12) layer and drain (13) layer with an inner extension (14,15) of lightly doped n-type layer into the gate region. The main isolated gate (GC) is situated over the gate region and the floating gate (GF) is situated over the lightly doped drain region. In charging the cell excess electrons pass to the extension zone and the floating command.

公开(公告)号：DE69728205T2

公开(公告)日：2005-02-17

申请号：DE69728205

申请日：1997-05-02

Applicant: ST MICROELECTRONICS SA

Inventor： PAPADAS CONSTANTIN

IPC: H01L21/3213 ,  H01L21/768 ,  H01L23/532

Abstract: The invention provides a method for producing wirings (67, 70, 75) and contacts (60) in an integrated circuit comprising the steps of: forming insulated gate components on a semiconductor substrate (10); applying a photo-reducible dielectric layer (80) to cover the substrate; etching holes (45, 50, 55) and forming contacts; photo-reducing the dielectric to increase its conductivity; covering the resulting structure with an interconnect layer (64); etching the interconnect layer to define wirings in electrical contact with the contacts (60); and oxidising the dielectric to reduce its conductivity.

公开(公告)号：DE69615449D1

公开(公告)日：2001-10-31

申请号：DE69615449

申请日：1996-05-15

Applicant: ST MICROELECTRONICS SA

Inventor： PAPADAS CONSTANTIN ,  NIKOLAIDIS THEODOROS

IPC: H01L27/04 ,  H01L21/822 ,  H01L21/8234 ,  H01L27/02 ,  H01L27/088 ,  H01L29/78

公开(公告)号：DE69728205D1

公开(公告)日：2004-04-29

申请号：DE69728205

申请日：1997-05-02

Applicant: ST MICROELECTRONICS SA

Inventor： PAPADAS CONSTANTIN

IPC: H01L21/3213 ,  H01L21/768 ,  H01L23/532

Abstract: The invention provides a method for producing wirings (67, 70, 75) and contacts (60) in an integrated circuit comprising the steps of: forming insulated gate components on a semiconductor substrate (10); applying a photo-reducible dielectric layer (80) to cover the substrate; etching holes (45, 50, 55) and forming contacts; photo-reducing the dielectric to increase its conductivity; covering the resulting structure with an interconnect layer (64); etching the interconnect layer to define wirings in electrical contact with the contacts (60); and oxidising the dielectric to reduce its conductivity.