公开(公告)号：JPH11243121A

公开(公告)日：1999-09-07

申请号：JP30020898

申请日：1998-10-21

Applicant: ST MICROELECTRONICS SA

Inventor： VALLET MICHEL

IPC: G01R1/06 ,  G01R31/28 ,  H01L21/66 ,  H01L21/822 ,  H01L27/04

Abstract: PROBLEM TO BE SOLVED: To enable a microprobe to be easily and automatically adjusted at a contact point by a method, wherein the contact point formed on the surface of a board and a guide means used for a test probe which moves on the surface of the board toward the contact point are provided. SOLUTION: A test region incorporated in a board is equipped with a nearly circular center contact point 14 formed of the surface of a metal small disk. The contact point 14 is surrounded by eight long and thin rectangular guide means (bosses) 16. The bosses 16 are arranged adjacent to the contact point 14 and directed to the center of the contact point 14 in the radial directions. The edges 16a of the bosses 16 which are directed toward the contact point 14 are arranged adequately separately from each other to give passages for a microprobe 20 to move on the surface of the board. Moreover, the edge of the microprobe 20 is connected electrically to the contact point 14.

公开(公告)号：FR2854731B1

公开(公告)日：2005-08-12

申请号：FR0305434

申请日：2003-05-05

Applicant: ST MICROELECTRONICS SA

Inventor： VALLET MICHEL ,  KRITTER SYLVAIN

IPC: G01R31/307 ,  H01L23/58 ,  H01L23/544

Abstract: The circuit (2) has an interconnection part (4) disposed on an active zone (3). The interconnection part has multiple metallization levels (5-12) and test pin (22) that is located in a metallization level situated under an upper metallization level (12) and located under supply lines. Signal interconnection lines are isolated between them and with respect to the test pin by a dielectric material. An independent claim is also included for a method of testing an integrating circuit.

公开(公告)号：FR2854731A1

公开(公告)日：2004-11-12

申请号：FR0305434

申请日：2003-05-05

Applicant: ST MICROELECTRONICS SA

Inventor： VALLET MICHEL ,  KRITTER SYLVAIN

IPC: G01R31/307 ,  H01L23/58 ,  H01L23/544

Abstract: The circuit (2) has an interconnection part (4) disposed on an active zone (3). The interconnection part has multiple metallization levels (5-12) and test pin (22) that is located in a metallization level situated under an upper metallization level (12) and located under supply lines. Signal interconnection lines are isolated between them and with respect to the test pin by a dielectric material. An independent claim is also included for a method of testing an integrating circuit.

公开(公告)号：FR2879295B1

公开(公告)日：2007-03-16

申请号：FR0413292

申请日：2004-12-14

Applicant: ST MICROELECTRONICS SA

Inventor： VALLET MICHEL ,  SARDIN PHILIPPE ,  PARRASSIN THIERRY ,  DUDIT SYLVAIN

IPC: G01R31/26

Abstract: The structure has a channel (80) provided between top of a commutation unit and a front side of an electronic integrated circuit. The channel guides photons towards the front side, where the photons are emitted by the commutation unit. The channel comprises a stack of metallizing rings (82-87) provided in respective bonding layers such that vias acts as a shield to stop escape of the photons from the channel between the rings. An independent claim is also included for an electronic integrated circuit comprising a test structure.

公开(公告)号：FR2783971B1

公开(公告)日：2002-08-23

申请号：FR9812249

申请日：1998-09-30

Applicant: ST MICROELECTRONICS SA

Inventor： VALLET MICHEL

IPC: G03F7/20 ,  G03F9/00 ,  H01L21/68 ,  H01L23/544 ,  H05K13/00

Abstract: A semiconductor circuit that includes components and registration features that are electrically isolated from the components. The registration features form projecting parts that are uniformly distributed in the form of a matrix over at least part of the external surface of the circuit so as to define adjacent registration areas. In a preferred embodiment, the semiconductor circuit also includes metal registration features that are produced in at least one metallization level of the circuit. Also provided is a method of adjusting a tool so as to put it into a particular position with respect to the surface of a semiconductor circuit that has registration features defining adjacent registration areas. According to the method, an at least partial topographic record of the registration features on the surface of the semiconductor circuit is produced, and the registration features of the topographic record are brought into coincidence with reference features of a reference drawing. The reference features of the reference drawing correspond to the registration features of the circuit. The position of the tool is adjusted with respect to at least some of the reference features or registration features.

公开(公告)号：FR2795870A1

公开(公告)日：2001-01-05

申请号：FR9908488

申请日：1999-07-01

Applicant: ST MICROELECTRONICS SA

Inventor： VALLET MICHEL ,  VINCENT EMMANUEL ,  HUGUES JEAN FRANCOIS

IPC: H01L21/768 ,  H01L23/528 ,  H01L23/525

Abstract: The semiconductor circuit (1) comprises electronic components or elements selectively connected and implemented at several levels, where at least two components or elements are connected to two respective portions of strip conductors (6,8; 7,9) belonging to the same level of metallisation (2); the two portions have adjacent parts situated in a zone (12,14) above which the circuit is free from electronic components or strip conductors. The circuit configuration is altered by making wells (15) in marked locations above zones (12,14) to expose the adjacent parts of strip conductors and to deposit a connection material (18,19) at the bottom of wells to electrically connect the portions of strip conductors and consequently the electronic components or elements. The adjacent parts of strip conductors are their extremities separated by a spacing which is at most equal to the width or thickness. At least one of electronic components is connected to another strip conductor (3) having a part situated in a marked zone above which the circuit is free from electronic components or strip conductors, where another well (17) is made to expose the part of strip conductor and to section the part in order to disconnect the components connected on two sides of sectioning (20). The making of wells (15,17), the deposition of connection material (18,19), the sectioning (20) and oxide deposition (21) are carried out by use of focused ion beam (FIB) technology.

公开(公告)号：DE69828136D1

公开(公告)日：2005-01-20

申请号：DE69828136

申请日：1998-10-20

Applicant: ST MICROELECTRONICS SA

Inventor： VALLET MICHEL

IPC: G01R1/06 ,  G01R31/28 ,  H01L21/66 ,  H01L21/822 ,  H01L27/04 ,  G01R31/316

公开(公告)号：FR2854730A1

公开(公告)日：2004-11-12

申请号：FR0305433

申请日：2003-05-05

Applicant: ST MICROELECTRONICS SA

Inventor： VALLET MICHEL

IPC: H01L23/528 ,  H01L23/544 ,  H01L21/768

Abstract: The circuit (1) has an interconnection level with suspended conductors (3), where a part of the suspended conductors presents an oriented L shape realized from non-parallel rectangles that are in mutual contact. The suspended conductors are aligned or oriented identically and are disposed at a level of a metallic terminal.

公开(公告)号：FR2879295A1

公开(公告)日：2006-06-16

申请号：FR0413292

申请日：2004-12-14

Applicant: ST MICROELECTRONICS SA

Inventor： VALLET MICHEL ,  SARDIN PHILIPPE ,  PARRASSIN THIERRY ,  DUDIT SYLVAIN

IPC: G01R31/26

Abstract: Une structure de test pour circuit électronique intégré ayant un substrat essentiellement plan recouvert d'une pluralité de couches de métallisation (M1-M7), comprend un élément de commutation (10) réalisé à la surface du substrat. Elle comprend en outre un tunnel (80) réalisé dans une (ou des) couche(s) couches de métallisation entre le dessus de l'élément de commutation et la face avant (15) du circuit intégré. Ce tunnel est adapté pour canaliser vers ladite face avant des photons émis par l'élément de commutation.

公开(公告)号：FR2783971A1

公开(公告)日：2000-03-31

申请号：FR9812249

申请日：1998-09-30

Applicant: ST MICROELECTRONICS SA

Inventor： VALLET MICHEL

IPC: G03F7/20 ,  G03F9/00 ,  H01L21/68 ,  H01L23/544 ,  H05K13/00

Abstract: Semiconductor circuit comprises a set of markers electrically insulated from electronic components and projecting from the surface of the circuit, uniformly spaced in the form of a matrix and determining the marking zones (8). The marking set comprises metallic patterns (5) formed on the last layer of metallization of the circuit and covered with an insulating layer (6) forming projecting parts (7). The procedure for tool positioning includes the topographic reading of at least a part of the marking pattern on the exterior surface, a comparison to a reference pattern, and the position control of a tool with respect to the adjacent reference or marking patterns. The marking patterns (5,7) have different forms and are spaced according to the structure of the circuit components; they comprise numerals and direction indicators. The marking patterns comprise arrows (5a, 7a) and wings (5b, 7b) indicating a common direction, e.g. 45 deg with respect to the matrix rows and columns. The procedure for the positioning of a tool is carried out by an electronic apparatus for controlled guiding of the tool by reading the marking patterns.