公开(公告)号：KR1020040046425A

公开(公告)日：2004-06-05

申请号：KR1020020074353

申请日：2002-11-27

Applicant: 한국전자통신연구원

Inventor： 박형일 ,  임인기 ,  정희범 ,  김종대

IPC: H01Q3/38

CPC classification number: H04B7/0854 ,  H04B7/086

Abstract: PURPOSE: A normalization apparatus is provided to reduce the size of hardware for system configuration and improve a real time processing speed. CONSTITUTION: A normalization apparatus comprises a multiplying unit for carrying out a multiplying operation required in a normalization process; a dividing unit for carrying out a dividing operation required in a normalization process through a binary log and subtracting operation; and a multiplexer(210) for synchronizing the signals received from a smart antenna receiver with a predetermined clock, and outputting the signals to the multiplying unit. The multiplying unit includes a binary log generator(220) for converting the signals input from the multiplexer into a binary log value and outputting the binary log value; a shift left(240) for outputting the output of the binary log generator into a double size; and a binary inverse log generator(250) for converting the output of the shift left into a binary inverse log value and outputting the binary inverse log value. The dividing unit includes a NORM binary log generator(270) for converting the NORM function value output from an adder into a binary log value and outputting the binary log value; a subtractor for subtracting the output of the NORM binary log generator from the output of a shift register(230); and a NORM binary inverse log generator(290) for converting the output of the subtractor into a binary inverse log value and outputting the binary inverse log value.

Abstract translation: 目的：提供一种归一化装置，以减小系统配置的硬件尺寸，提高实时处理速度。 构成：归一化装置包括：乘法单元，用于执行归一化处理中所需的乘法运算; 分割单元，用于通过二进制对数和减法运算执行归一化处理中所需的分割操作; 以及用于将从智能天线接收机接收的信号与预定时钟同步的多路复用器（210），并将该信号输出到乘法单元。 乘法单元包括用于将从多路复用器输入的信号转换成二进制对数值并输出二进制对数值的二进制对数生成器（220） 左移（240），用于将二进制日志生成器的输出输出为双倍大小; 以及用于将左移的输出转换为二进制反向对数值并输出二进制反向对数值的二进制反向对数生成器（250）。 分割单元包括NORM二进制对数发生器（270），用于将从加法器输出的NORM函数值转换为二进制对数值并输出二进制对数值; 减法器，用于从移位寄存器（230）的输出中减去所述NORM二进制对数生成器的输出; 以及用于将减法器的输出转换为二进制反向对数值并输出二进制反向日志值的NORM二进制逆对数生成器（290）。

公开(公告)号：KR1020040041716A

公开(公告)日：2004-05-20

申请号：KR1020020069567

申请日：2002-11-11

Applicant: 한국전자통신연구원

Inventor： 변경진 ,  정희범 ,  김경수 ,  김종대

IPC: G10L19/12 ,  G10L19/107

CPC classification number: G10L19/107 ,  G10L2019/0013

Abstract: PURPOSE: A method of searching a codebook of a code excited linear prediction (CELP) vocoder using an algebraic codebook is provided to search the algebraic codebook with a small amount of calculations using a search tree restricting method. CONSTITUTION: A method of searching an algebraic codebook of an algebraic CELP vocoder using a depth-first tree search method includes a step(100) of searching up to a specific level of trees in order to predict a tree where an optimum pulse is positioned, a step(200) of selecting a predetermined tree according to the search result and removing other trees, and a step(300) of searching only the selected tree to select an optimum algebraic code.

Abstract translation: 目的：提供使用代数码本搜索代码激励线性预测（CELP）声码器的码本的方法，使用搜索树限制方法以少量的计算来搜索代数码本。 构成：使用深度优先树搜索方法来搜索代数CELP声码器的代数码本的方法包括：搜索特定级别的树以便预测最佳脉冲所在的树的步骤（100） 根据搜索结果选择预定树并去除其他树的步骤（200）;以及仅搜索所选树以选择最佳代数代码的步骤（300）。

公开(公告)号：KR100422806B1

公开(公告)日：2004-03-16

申请号：KR1020010065158

申请日：2001-10-22

Applicant: 한국전자통신연구원

Inventor： 김귀동 ,  정희범

IPC: H03K19/00

Abstract: PURPOSE: A current controlled variable delay circuit is provided to have low phase noise and a high speed switching. CONSTITUTION: The current controlled variable delay circuit comprises a variable current source(500), and a switching transistor part(100) forming a current path between the variable current source and one of the first and the second differential output signal(+Vout,-Vout) of the first or the second potential level in response to the first and the second differential input signal(V+,V-). A differential signal sensing part(200) generates the first and the second differential output signal by amplifying a different between the first and the second differential input signal in response to an output of the switching transistor part and operates in a saturated region. A positive feedback amplification part(300) increases a sensing speed of the differential signal sensing part by receiving an output of the differential signal sensing part as an input. And a potential level decreasing part(400) reduces noise of the first and the second differential output signal by reducing a potential difference between the first and the second differential output signal, and increases a response speed of the first or the second differential output signal responding to the first and the second differential input signal.

Abstract translation: 目的：提供电流控制的可变延迟电路以具有低相位噪声和高速切换。 构成：电流控制可变延迟电路包括可变电流源（500）和形成可变电流源与第一和第二差分输出信号（+ Vout， - 响应于第一和第二差分输入信号（V +，V-），输出第一或第二电位电平。 差分信号感测部分（200）响应于开关晶体管部分的输出通过放大第一差分输入信号和第二差分输入信号之间的差而产生第一差分输出信号和第二差分输出信号，并且操作在饱和区中。 正反馈放大部分（300）通过接收差分信号感测部分的输出作为输入来增加差分信号感测部分的感测速度。 并且电位降低部（400）通过减小第一和第二差分输出信号之间的电位差来减小第一和第二差分输出信号的噪声，并且增加第一或第二差分输出信号响应的响应速度 到第一和第二差分输入信号。

公开(公告)号：KR100377477B1

公开(公告)日：2003-03-26

申请号：KR1019990037893

申请日：1999-09-07

Applicant: 한국전자통신연구원 ,  주식회사 케이티

Inventor： 송원철 ,  정희범 ,  김귀동 ,  김성도

IPC: H03B5/12

Abstract: PURPOSE: A voltage-controlled oscillator having linear characteristic is provided to make a variation rate uniform without regard to a control voltage, so improve the characteristic of PLL. CONSTITUTION: The device includes a voltage-to-current converter(110) for converting an input control voltage into current, a current providing unit(120) for providing the converted current to an oscillator(130), and a voltage restricting unit(140) for restricting the voltage of the oscillator. The oscillator accepts the converted current to oscillate. The voltage-to-current converter has a buffer for compensating for a threshold voltage at the input port to operate normally from the initial operation state. The converter operates a transistor taking charge of conversion in a linear area to make a voltage/current conversion gain be linear.

Abstract translation: 目的：提供具有线性特性的电压控制振荡器，使变化率不受控制电压影响，从而改善PLL的特性。 该装置包括用于将输入控制电压转换为电流的电压 - 电流转换器（110），用于将转换后的电流提供给振荡器（130）的电流提供单元（120），以及电压限制单元 ）用于限制振荡器的电压。 振荡器接受转换后的电流进行振荡。 电压 - 电流转换器具有缓冲器，用于补偿输入端口处的阈值电压以从初始操作状态正常操作。 转换器在线性区域中操作负责转换的晶体管以使电压/电流转换增益为线性。

公开(公告)号：KR100373322B1

公开(公告)日：2003-02-25

申请号：KR1020000086651

申请日：2000-12-30

Applicant: 한국전자통신연구원

Inventor： 서혜주 ,  권종기 ,  김귀동 ,  정희범

IPC: H03H11/02

Abstract: PURPOSE: An automatic frequency tuning circuit for correcting an influence of offset for transistor conductance-capacitor filter is provided to control correctly a band frequency of a filter by correcting offset of a tuning circuit. CONSTITUTION: A reference power supply portion(100) provides reference power. A Gm amplifier(5) has. The first integrator(200) has a Gm amplifier(5) having the same as a Gm value of a controlled filter in order to generate periodically charge voltage and discharge voltage proportional to offset of the Gm amplifier(5) in response to the reference power. The second integrator(300) has a Gm amplifier(16) having the same as a Gm value of a controlled filter in order to generate periodically charge voltage and proportional to offset of the Gm amplifier(16) in response to the output voltage(Vo1) of the first integrator(200) and discharge voltage proportional to offset of the Gm amplifier(16) in response to the reference power. A sampling portion(400) samples periodically the output voltage of the second integrator(300). An output portion(500) outputs the sampled voltage of the sampling portion(400) as a tuning signal and feed back the tuning signal to the Gm amplifier(5) in order to control a transfer conductance value of the Gm amplifier(5).

Abstract translation: 目的：提供一种用于校正晶体管电导电容器滤波器的偏移影响的自动频率调谐电路，以通过校正调谐电路的偏移来正确地控制滤波器的频带频率。 构成：参考电源部分（100）提供参考功率。 一个Gm放大器（5）具有。 第一积分器（200）具有与受控滤波器的Gm值相同的Gm放大器（5），以响应于参考功率产生周期性的充电电压和与Gm放大器（5）的偏移成比例的放电电压 。 第二积分器（300）具有与受控滤波器的Gm值相同的Gm放大器（16），以便响应于输出电压（Vo1）产生周期性充电电压并与Gm放大器（16）的偏移成比例 ）以及响应于所述参考功率而放电的电压，所述放电电压与所述Gm放大器（16）的偏移量成比例。 采样部分（400）周期性地采样第二积分器（300）的输出电压。 输出部分（500）输出采样部分（400）的采样电压作为调谐信号，并将调谐信号反馈到Gm放大器（5），以便控制Gm放大器（5）的传输电导值。

公开(公告)号：KR1020010076615A

公开(公告)日：2001-08-16

申请号：KR1020000003866

申请日：2000-01-27

Applicant: 한국전자통신연구원

Inventor： 권종기 ,  오창준 ,  이종렬 ,  송원철 ,  정희범 ,  조한진

IPC: H03D7/10

Abstract: PURPOSE: A frequency mixing circuit improved DC offset characteristic by using high bandwidth passing characteristic is provided to obtain proper DC offset characteristic regardless of effecting from an input signal voltage value, and minimize the power consumption due to a simple structure. CONSTITUTION: A voltage-current conversion section(20) amplifies an input voltage signal of a differential type provided from an input signal and a reference providing section(10), and converts the input voltage signal into a differential output current. A frequency mixing section(30) mixes the converted current provided from the voltage-current conversion section(20) with an applied clock signal from an outside. An output signal generation section(40) generates an output voltage signal through an output load resistor after receiving the converted current from frequency mixing section(30).

Abstract translation: 目的：通过使用高带宽通过特性改善DC偏移特性，以获得适当的直流偏移特性，而不管输入信号电压值如何，并且由于结构简单而使功耗最小化。 构成：电压电流转换部（20）放大从输入信号提供的差分类型的输入电压信号和参考提供部（10），并将输入电压信号转换成差分输出电流。 频率混合部分（30）将从电压电流转换部分（20）提供的转换电流与外部施加的时钟信号进行混合。 输出信号生成部（40）在从频率混合部（30）接收到转换后的电流之后，通过输出负载电阻生成输出电压信号。

公开(公告)号：KR1020010073947A

公开(公告)日：2001-08-03

申请号：KR1020000003156

申请日：2000-01-24

Applicant: 한국전자통신연구원 ,  브이케이 주식회사

Inventor： 김귀동 ,  정희범

IPC: H03L7/00

Abstract: PURPOSE: A high speed and low voltage charge pump of a phase synchronous loop is provided to make the output load of a charge pump high and to make the size of the output current changed automatically according to the loop filter voltage. CONSTITUTION: The high speed and low voltage charge pump(200) of the phase synchronous loop includes many transistors. A source of the charge transistor(M11) is connected to the power voltage(VCC). The gate and drain of a charge bias transistor(M12) are connected to the gate of the charge transistor(M11). The drain of a charge switching transistor(M7) is connected to the drain of the charge bias transistor(M12). The source of a P channel MOS transistor(M10) is connected to the drain of the charge transistor(M11) and the gate and drains are connected the output node(Icm). The gate and drains of an N channel MOS transistor diode(M9) is connected to the output node(Icm). The gate of a discharge switching transistor(M8) is connected to the discharge input signal(DP) and the drain is connected to the source of the N channel MOS transistor diode(M9) and the source of that is connected to the node a. The drain of a discharge bias transistor(M1) is connected to the node a and the source of that is connected to the bias(VSS).

Abstract translation: 目的：提供相位同步环路的高速和低压电荷泵，使电荷泵的输出负载较高，并根据环路滤波器电压自动改变输出电流的大小。 构成：相位同步回路的高速和低压电荷泵（200）包括许多晶体管。 充电晶体管（M11）的源极连接到电源电压（VCC）。 电荷偏置晶体管（M12）的栅极和漏极连接到充电晶体管（M11）的栅极。 充电开关晶体管（M7）的漏极连接到电荷偏置晶体管（M12）的漏极。 P沟道MOS晶体管（M10）的源极连接到充电晶体管（M11）的漏极，栅极和漏极连接在输出节点（Icm）上。 N沟道MOS晶体管二极管（M9）的栅极和漏极连接到输出节点（Icm）。 放电开关晶体管（M8）的栅极连接到放电输入信号（DP），漏极连接到N沟道MOS晶体管二极管（M9）的源极，其源极连接到节点a。 放电偏压晶体管（M1）的漏极连接到节点a，其源极连接到偏置（VSS）。

公开(公告)号：KR100283626B1

公开(公告)日：2001-03-02

申请号：KR1019980052952

申请日：1998-12-03

Applicant: 주식회사 케이티 ,  한국전자통신연구원

Inventor： 김진영 ,  김성도 ,  정희범

IPC: H04L7/00

Abstract: 본 발명의 목적은 고속 데이터 전송에서, 전송 선로가 이상적이지 못하기 때문에 나타나는 지터를 간단한 쉬프트 레지스터로 구성된 완충 버퍼를 이용하여 흡수하고, 동시에, 입력 직렬 데이터에서 추출한 클럭에 독립적인 외부 입력 클럭을 이용하여 데이터를 완충 버퍼에서 읽어내며, 또한 이 클럭을 이용하여 입력 직렬 데이터의 지터가 존재하지 않는 병렬 데이터로 출력하도록 하는 지터 흡수 및 직렬-병렬 변환장치를 제공함에 있다. 이와같은 본 발명은 완충 버퍼(elastic buffer)와 직렬-병렬 변환 장치를 결합함으로써, 고속 회로에서 중요한 요소인 간단한 회로 구성으로 구현이 가능하고, 디지털 회로로만 구성되어 있기 때문에 직접회로가 가능하며, 쉬프트레지스터와 타이밍 신호 장치만 변경하면 슬립 비트(slip bit)수를 증가시킬 수 있는 효과가 있다.

公开(公告)号：KR100248426B1

公开(公告)日：2000-03-15

申请号：KR1019970070330

申请日：1997-12-19

Applicant: 한국전자통신연구원 ,  주식회사 케이티

Inventor： 김성도 ,  정희범 ,  김귀동 ,  송원철 ,  김경수

IPC: H04L12/28

Abstract: 본 발명은 SDH 기반의 ATM 통신에서 STM-n(Synchronous Transport Module-n, n=1,4,16..) 타이머의 오류 검출 및 자동 복구를 위한 리셋 신호 생성장치에 관한 것이다. 본 발명은 두 클럭원간의 스위칭 동작을 비트동기장치의 LOS(Loss Of Signal) 정보로부터 감지하고 이 스위칭으로 인하여 디지털회로가 영향을 받았는지를 OOF(Out Of Frame)와 FPID(Framing Word Detection Indication Signal) 정보로부터 판단한 후에 비정상적인 동작상태로 판단되면 리셋신호를 생성하여 STM-n(n=1,4,16) 프레임 데이터의 타이머회로를 초기화시킴으로써 클럭 글리치에 의한 비정상적인 동작상태에서 자동적으로 복구할 수 있도록 고안된 STM-n(n=1,4,16) 프레임 데이터 처리를 위한 타이머회로의 오류검출 및 자동복구를 위한 리셋신호 생성장치에 관한 것이다.

公开(公告)号：KR1019980049370A

公开(公告)日：1998-09-15

申请号：KR1019960068071

申请日：1996-12-19

Applicant: 한국전자통신연구원 ,  주식회사 케이티

Inventor： 전인산 ,  정희범 ,  송원철

IPC: H04L1/00 ,  H04L12/26 ,  H04L12/70

Abstract: 본 발명은 ATM 셀 전송에 기초한 동기식 디지털 계층(SDH)을 집적회로로 구현하는데 효과적인 헤더오류정정(HEC)의 구조에 관한 것으로서, 종래의 155Mbps SDH에서 HEC의 기본적인 구조는 8비트로 구성된 ATM셀을 처리하도록 되었지만 622Mbps SDH에서 ATM셀은 16비트 구조를 가지고 있어 16비트로 구성된 HEC 구조가 필요한 문제가 있으므로 상기 문제점을 해결하기 위해 본 발명의 HEC는 ATM 셀의 헤더 5바이트에서 발생하는 오류를 정정하기 위하여 부호화하고 복호화하는 기능을 수행하며, 이 때 생성다항식 g(x)=x
8 +x
2 +x+1 을 사용함으로써, 5바이트의 셀 헤더에서 발생하는 오류 중 1비트를 정정할 수 있고 다중오류를 검출할 수 있는 능력을 가지고 있으므로 16비트로 구성된 ATM 셀을 처리하기 위한 새로운 HEC 구조를 제시하여 ATM 셀 동기를 맞추는데 효율적인 구조를 가 지고 있다.