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公开(公告)号：KR1020010076615A
公开(公告)日：2001-08-16
申请号：KR1020000003866
申请日：2000-01-27
Applicant: 한국전자통신연구원
IPC: H03D7/10
Abstract: PURPOSE: A frequency mixing circuit improved DC offset characteristic by using high bandwidth passing characteristic is provided to obtain proper DC offset characteristic regardless of effecting from an input signal voltage value, and minimize the power consumption due to a simple structure. CONSTITUTION: A voltage-current conversion section(20) amplifies an input voltage signal of a differential type provided from an input signal and a reference providing section(10), and converts the input voltage signal into a differential output current. A frequency mixing section(30) mixes the converted current provided from the voltage-current conversion section(20) with an applied clock signal from an outside. An output signal generation section(40) generates an output voltage signal through an output load resistor after receiving the converted current from frequency mixing section(30).
Abstract translation: 目的：通过使用高带宽通过特性改善DC偏移特性，以获得适当的直流偏移特性，而不管输入信号电压值如何，并且由于结构简单而使功耗最小化。 构成：电压电流转换部（20）放大从输入信号提供的差分类型的输入电压信号和参考提供部（10），并将输入电压信号转换成差分输出电流。 频率混合部分（30）将从电压电流转换部分（20）提供的转换电流与外部施加的时钟信号进行混合。 输出信号生成部（40）在从频率混合部（30）接收到转换后的电流之后，通过输出负载电阻生成输出电压信号。
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公开(公告)号：KR100283619B1
公开(公告)日：2001-03-02
申请号：KR1019980052969
申请日：1998-12-03
Applicant: 한국전자통신연구원
IPC: H03J3/00
Abstract: 본 발명은 튜닝 회로에 관한 것이며, 특히, Gm-C 타입의 연속-시간 (continuous-time) 필터에서, 공정 변이(variation)에 따른 차단(cutoff) 주파수의 변동 폭을 최소한으로 줄이기 위해 정확한 Gm 값을 만들어 낼 수 있도록 하는 연속-시간 필터를 위한 주파수 튜닝 회로를 제공하는 데 그 목적이 있다.
본 발명에 따르면, 제1 기준전압으로부터 제1 소정값까지 방전되는 신호와 제2 기준전압으로부터 제2 소정값까지 충전된 신호를 생성하기 위한 적분 수단; 상기 적분 수단에 포함된 Gm셀로부터 옵셋 전압에 따라 증배된 전류를 입력받고, 포함하고 있는 Gm셀의 출력 노드와 입력 노드에 귀환 경로를 제공함으로써 Gm셀의 옵셋 전압을 샘플링하기 위한 옵셋 샘플링 수단; 외부로부터 입력된 클럭을 분주하여 기준 신호를 생성하며, 상기 적분 수단으로부터 입력된 제1 기준전압으로부터 제1 소정값까지 방전되는 신호와 제2 기준전압으로부터 제2 소정값까지 충전된 신호를 입력받아 실제 교차지점과 목표로 하는 교차지점을 비교하기 위한 신호를 생성하기 위한 비교 신호 발생 수단; 및 상기 비교 신호 발생 수단으로부터 기준 신호와 비교하기 위한 신호를 입력받아 위상을 검출하여 상기 적분 수단과 상기 옵셋 샘플 수단의 Gm값을 조정할 수 있는 제어 신호를 생성하기 위한 제어 수단을 포함하여 이루어진 주파수 튜닝 회로가 제공된다.-
公开(公告)号：KR1020000038107A
公开(公告)日：2000-07-05
申请号：KR1019980052969
申请日：1998-12-03
Applicant: 한국전자통신연구원
IPC: H03J3/00
CPC classification number: H03H11/0422 , H03L7/06
Abstract: PURPOSE: A frequency tuning circuit used for a continuous-time filter is provided to reduce the fluctuation of the cutoff frequency by creating an accurate Gm value. CONSTITUTION: A frequency tuning circuit has an integration device(120) for tuning a Gm cell(126). The integration device(120) receives an increased current according to an offset voltage and generates an increased current by receiving first and second basis voltages. An offset sampling device(110) is provided to receive the increased current from the Gm cell(126) thereby sampling the offset voltage of the Gm cell(126). The offset sampling device(110) provides a return passage to the output and input nodes. A comparing signal generating device(140) is provided to generates a basis signal. The comparing signal generating device(140) generates a signal for comparing a cross position with a target cross position by receiving a discharge signal and a filling signal. A control device is provided to generate a control signal so as to adjust the Gm value of the integration device(120) and the offset sample device(110).
Abstract translation: 目的：提供用于连续时间滤波器的频率调谐电路，通过创建精确的Gm值来减少截止频率的波动。 构成：频率调谐电路具有用于调谐Gm单元（126）的集成装置（120）。 积分装置（120）根据偏移电压接收增加的电流，并通过接收第一和第二基准电压来产生增加的电流。 提供偏移采样装置（110）以接收来自Gm单元（126）的增加的电流，从而对Gm单元（126）的偏移电压进行采样。 偏移采样装置（110）向输出和输入节点提供返回通道。 提供比较信号发生装置（140）以产生基准信号。 比较信号发生装置（140）通过接收放电信号和填充信号产生用于比较交叉位置与目标十字位置的信号。 提供控制装置以产生控制信号，以便调整积分装置（120）和偏移采样装置（110）的Gm值。
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公开(公告)号：KR1019980039485A
公开(公告)日：1998-08-17
申请号：KR1019960058509
申请日：1996-11-27
Applicant: 한국전자통신연구원
IPC: G11C5/14
Abstract: 1. 청구범위에 기재된 발명이 속한 기술분야
집적회로 내장형 공급전원 지연회로.
2. 발명이 해결하려고 하는 기술적 과제
그 구조가 단순하고, 커패시턴스 또는 MOS 커패시턴스에서의 전류 방전에 의한 지연 및 음 되돌림(negative feedback)에 의한 재생 동작으로 일정 시점후 매우 안정된 공급전원을 인가하도록 하고자 함.
3. 발명의 해결방법의 요지
공급전압을 충전하는 수단과 전류를 공급하는 수단과 충전수단의 출력값을 반전시키는 수단과 반전수단의 출력 값에 의해 제어되어 전류공급수단의 출력을 스위칭하는 수단과 스위칭수단의 제어를 받아 충전수단의 출력 값을 방전시키는 전류반복수단과 반전수단의 출력값에 의해 제어되어 충전수단의 출력 값을 접지전위로 변환시키는 전위값 변환수단, 및 반전수단의 출력값을 입력받아 반전, 비반전된 신호를 출력하는 버퍼링수단을 구비함
4. 발명의 중요한 용도
안정된 공급전원을 요하는 집적회로에 이용됨.-
公开(公告)号：KR1019960008216B1
公开(公告)日：1996-06-20
申请号：KR1019930027340
申请日：1993-12-11
Applicant: 한국전자통신연구원
IPC: H03F3/183
Abstract: a main operational amplifier(10) for generating a differential output signal by charging and discharging two capacitors(C1, C2) of an output terminal with a supply voltage(Vdd) responding to a differential input signal; an auxiliary operational amplifier(20) for generating a monitor signal to show a operating mode of the main amplifier; and a transconductor(30) for increasing a slew rate by being turned off when the monitoring signal indicates a small signal mode, or by supplying predetermined current(I19) to the main operational amplifier when a monitoring signal indicates a large signal mode; thereby achieving a high speed operational amplifier.
Abstract translation: 主运算放大器（10），用于通过响应于差分输入信号的电源电压（Vdd）对输出端子的两个电容器（C1，C2）进行充电和放电来产生差分输出信号; 辅助运算放大器（20），用于产生监视信号以显示主放大器的工作模式; 以及跨监视器（30），当监视信号表示小的信号模式时，通过关闭所述转换速率，或者当监控信号表示大的信号模式时，通过向主运算放大器供给预定的电流（I19） 从而实现高速运算放大器。
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公开(公告)号：KR1020010047751A
公开(公告)日：2001-06-15
申请号：KR1019990052110
申请日：1999-11-23
Applicant: 한국전자통신연구원
IPC: H03F3/04
CPC classification number: H03G1/0029 , H03F3/45188 , H03F2203/45458 , H03F2203/45702
Abstract: PURPOSE: A CMOS variable gain AMP and a method for controlling thereof are provided to supply a CMOS variable gain AMP with the wide input range and the characteristics of the excellent high frequency operation. CONSTITUTION: In the CMOS variable gain AMP and the method for controlling thereof, an input differential amp, a bias current controlling portion, an operation point controlling portion and the load resistance(R1, R2) are included. The input differential AMP is composed of two input differential transistors(M1, M2), in which the input voltage is applied. The bias current controlling portion is composed of a transistor(M5), the drain of which is connected to the source of the input differential transistors(M1, M2). The operation point controlling portion is composed of the transistors(M3, M4), each source of which is connected to the drain of the input differential transistors(M1, M2), and the control voltage(Vcon) terminal is connected to the gate connected in common. Each load resistance(R1, R2) is connected to the drain of the transistors(M3, M4) and makes the output voltage(Von, Vop) be caught on the connecting point.
Abstract translation: 目的：提供CMOS可变增益放大器及其控制方法，以提供具有宽输入范围和优异高频操作特性的CMOS可变增益AMP。 构成：在CMOS可变增益AMP及其控制方法中，包括输入差分放大器，偏置电流控制部分，工作点控制部分和负载电阻（R1，R2）。 输入差分AMP由施加输入电压的两个输入差分晶体管（M1，M2）组成。 偏置电流控制部分由晶体管（M5）组成，其漏极连接到输入差分晶体管（M1，M2）的源极。 操作点控制部分由晶体管（M3，M4）组成，其每个源极连接到输入差分晶体管（M1，M2）的漏极，并且控制电压（Vcon）端子连接到栅极连接 共同点 每个负载电阻（R1，R2）连接到晶体管（M3，M4）的漏极，并使输出电压（Von，Vop）被捕获在连接点上。
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公开(公告)号：KR100276083B1
公开(公告)日：2000-12-15
申请号：KR1019970071614
申请日：1997-12-22
Applicant: 한국전자통신연구원
IPC: H03L7/00
Abstract: PURPOSE: A frequency dividing device for low noise of frequency composer is provided to perform low phase noise property by adding extra latch to output end of frequency divider and isolating power source line from other lines. CONSTITUTION: A time delay circuit(100) delays input clock signal for a time. A frequency divider(200) divides signal delayed in the time delay circuit(100). A D-flipflop(300) is connected to output side of the frequency divider(200), and takes input clock signal inputted to the time delay circuit(100) as clock and eliminates delay time of the frequency divider(200) according to input signal of the frequency divider(200). The delay time of the time delay circuit(100) is prior to the time latched in the D-flipflop(300) in case that total input signal is output in the frequency divider(200).
Abstract translation: 目的：提供频率合成器低噪声的分频装置，通过向分频器的输出端增加额外的锁存器，并将电源线与其他线路隔离来提供低相位噪声性能。 时间延迟电路（100）延迟输入时钟信号一段时间。 分频器（200）对延迟电路（100）中延迟的信号进行分频。 D触发器（300）连接到分频器（200）的输出侧，并将输入到时间延迟电路（100）的输入时钟信号作为时钟，并根据输入消除分频器（200）的延迟时间 分频器（200）的信号。 在分频器（200）中输出总输入信号的情况下，时间延迟电路（100）的延迟时间在D触发器（300）中锁存的时间之前。
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公开(公告)号：KR100268648B1
公开(公告)日：2000-10-16
申请号：KR1019970032659
申请日：1997-07-14
IPC: H03H9/46
CPC classification number: H03H11/04
Abstract: PURPOSE: A low frequency filter is provided to allow a low frequency filter having a cut frequency(3fdB) in a very low frequency(within several hundreds of Hz) to be built into a chip by using an active resistor having a very large resistance and a capacitor of several pF. CONSTITUTION: A low frequency filter includes a capacitor of a small capacity connected between an input terminal and an output terminal of the low frequency filter. A filter circuit(110A) includes an active resistor having a transistor of a dynamic resistance characteristic inputted to the output terminal of the capacitor and operating as a current source. The filter circuit(110A) functions to filter the inputted signal and to cut low frequency signals. A bias circuit(110B) is connected to an active resistor of the filter circuit(110A) and negative-feedbacks an output voltage of the active resistor being an output voltage of the filter circuit(110A) by means of the transistor of a dynamic resistance characteristic operating as the current source of a structure such as the active resistor. The filter circuit(110A) and the bias circuit(110B) are built in a semiconductor chip.
Abstract translation: 目的：提供一种低频滤波器，通过使用具有非常大电阻的有源电阻器，将具有非常低频率（几百Hz）内的切割频率（3fdB）的低频滤波器内置到芯片中， 几个pF的电容器。 构成：低频滤波器包括连接在低频滤波器的输入端子和输出端子之间的小容量电容器。 滤波器电路（110A）包括具有输入到电容器的输出端子并作为电流源工作的动态电阻特性的晶体管的有源电阻器。 滤波器电路（110A）用于对输入信号进行滤波并切断低频信号。 偏置电路（110B）连接到滤波电路（110A）的有源电阻器，并通过动态电阻晶体管对有源电阻器的输出电压作为滤波电路（110A）的输出电压进行负反馈 特性作为诸如有源电阻器的结构的电流源操作。 滤波器电路（110A）和偏置电路（110B）内置在半导体芯片中。
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