公开(公告)号：JPS57162545A

公开(公告)日：1982-10-06

申请号：JP4636781

申请日：1981-03-31

Applicant: FUJITSU LTD

Inventor： MATSUDA TAKASHI ,  MITA TERUYOSHI

IPC: H04J3/06 ,  H04J3/17 ,  H04M11/06

Abstract: PURPOSE:To realize a change of speed of transmission, by turning on and transmitting the control signal at the transmitting side when the signal in the data region is significant and fetching the signal in the data region after regarding it significant when the control signal is turned on at the receiving side. CONSTITUTION:At a transmitting station A, the series transmitting data DS is supplied to an SP converter 3 by the timing pulse (a) and then converted into a parallel data signal (b) to be supplied to a multiplexing part 5. At the part 5, the data information signal D1 including the signal (b) and the control signal (c) is multiplexed along with another signal D2 and a sound signal S1, etc. to be transmitted in the form of a transmitting frame signal (d). At the receiving side, the signal (d) is supplied to a clock extracting circuit 6, a receiving timing circuit 7 and an SP converter 8 respectively. On the other hand, the control signal in the transmission channel of the signal (d) is extracted at an AND gate 10 and by the latch timing signal (e) given from a circuit 7 to be applied a speed converting circuit 9 in the form of the latch timing signal (h). The signal (h) is set at a high level only when the control signal is on, and an output (f) of the converter 8 is fed into the circuit 9.

公开(公告)号：JPS5775040A

公开(公告)日：1982-05-11

申请号：JP15118980

申请日：1980-10-28

Applicant: Fujitsu Ltd

Inventor： IIJIMA KOUJI ,  MITA TERUYOSHI

IPC: H04B10/27 ,  H04B10/00 ,  H04B10/07 ,  H04B10/077 ,  H04B10/079 ,  H04B10/275 ,  H04B10/524 ,  H04B17/00

CPC classification number: H04B10/079 ,  H04B10/6931

Abstract: PURPOSE:To prevent a communication fault from occurring, by detecting degradation of the light emitting element of the optical transmitter of the preceeding station by respective node stations, which constitute an optical communication loop network, and a supervisory control station to transmit an alarm signal. CONSTITUTION:In each node station and a supervisory control station, the optical signal from an optical signal input terminal 10 is converted to an electric signal in a light receiving part 1, and the signal is taken out to an output terminal 1 through an amplifier 3 and a waveform shaping circuit 4. A part of this signal is applied to a light receiving level monitor part 7 through a peak-to-peak value detecting circuit 6 and an automatic gain adjusting circuit 5. At this time, since the photodetector has the characteristic changed by temperature, it is corrected by a temperature correcting circuit 8. When the photodetector is degraded and the level is lowered in a certain degree, an alarm circuit 9 transmits an alarm to an alarm output terminal 12. The time slot issued always for monitor is provided with one bit for insertion of the local address and the level alarm to transmit this alarm.

Abstract translation: 目的：通过检测构成光通信环路网络的各个节点站的前一站的光发射机的发光元件的劣化以及用于发送报警信号的监控控制站，防止发生通信故障。 构成：在每个节点站和监控站中，来自光信号输入端子10的光信号在光接收部分1中被转换为电信号，并且该信号通过放大器3被取出到输出端1 和波形整形电路4.该信号的一部分通过峰 - 峰值检测电路6和自动增益调整电路5施加到光接收电平监视器部分7.此时，由于光电检测器具有 特性由温度改变，由温度校正电路8校正。当光电检测器劣化并且在一定程度上降低电平时，报警电路9向报警输出端子12发送报警。始终为 监视器提供一位用于插入本地地址和级别报警以传送此报警。

公开(公告)号：JPS5711562A

公开(公告)日：1982-01-21

申请号：JP8706580

申请日：1980-06-26

Applicant: FUJITSU LTD

Inventor： KITANO YOSHIHIRO ,  SUZUKI YOUICHI ,  MITA TERUYOSHI

IPC: H04L12/42

Abstract: PURPOSE:To improve the utility of a packet, by preventing the transmission of useless packet to a data transmission line. CONSTITUTION:The first packet 12 transmitted from a transmission PX0 is received at a reception PX2, and the PX2 transmit a reception signal 14-1 to the PX0. The PX0 receives the signal 14-1 and transmits the fianl packet 13 to the PX2. The PX2 transmits a reception signal 14-2, when receptionable. The PX2 receiving the signal 14-2 does not transmit a reaction conforming signal and processes this packet as a vacant packet. On the other hand, when the data transfer between the reception PX2 and the sub-system SS5 is finished, the PX2 describes the response to the vacant packet and transmits a response packet signal 15-1 to the PX0. The PX0 transmits the reception of response to the PX2 and informs the end of the data transmission to the subsystem SS1.

公开(公告)号：JPS5690337A

公开(公告)日：1981-07-22

申请号：JP16900579

申请日：1979-12-25

Applicant: FUJITSU LTD

Inventor： SUZUKI YOUICHI ,  MITA TERUYOSHI

IPC: G06F13/00

Abstract: PURPOSE:To make it unnecessary to provide a control signal line between subsystems, by using in common a regular data transfer line between the subsystems, and the transfer line of the system control signal, in a compound computer system. CONSTITUTION:The control subsystem SS stores in the RAM11 the information for controlling other subsystem SS, and the data channel unit 12 sends it out to the data highway station 2 through the information transfer line 4 in the same way as the conventional data transition. The station 2 sends out this information onto the data highway 3. On the other hand, in the subsystem SS to be controlled, the command circuit 21 discrimenates the control signal from the control subsystem, and controls through the control signal line 5 the CPU stop signal line 19, the CPU start signal line 20, the electric power source closing line, etc. As a result, in the subsystem to be controlled, start/stop of the CPU, close/cut-off of the electric power source, etc. are executed. In this way, not only a regular data but also a control signal are sent out onto the highway 3, and the transfer line is used in common.

公开(公告)号：JPS5660142A

公开(公告)日：1981-05-23

申请号：JP13616779

申请日：1979-10-22

Applicant: FUJITSU LTD

Inventor： KITANO YOSHIHIRO ,  SUZUKI YOUICHI ,  MITA TERUYOSHI

IPC: G06F13/00 ,  H04L12/437

Abstract: PURPOSE:To make it rapid and accurate find a defective node by providing the header of a frame with a response part having response areas as many as nodes and by making it possible to know states of all nodes only by checking the response part through a supervisory device. CONSTITUTION:To signal transmission line (l), highway supervisory device SV and all nodes PX0-PXn are connected and to respective nodes PX0-PXn, sub systems SOa, SOb...Sna, and Snb are connected, constituting the data highway. The frame header of a unit frame for information flowing via this transmission line (l) is provided with response part NERR through which the error occurrence state of a node can be supervised by device SV all the time, and this response part NERR consists of response areas 0-7 as many as nodes PX0-PXn. When those areas 0-7 are sent out of device SV, all bits are set to 0 and when the frame reaches respective nodes PX0-PXn, 1 for normal operation or 0 for error detection is written in respective own response areas, so that device SV will be enabled to supervise all nodes PX0-PXn all the time.

公开(公告)号：JPS55128949A

公开(公告)日：1980-10-06

申请号：JP3677679

申请日：1979-03-28

Applicant: FUJITSU LTD

Inventor： KITANO YOSHIHIRO ,  SUZUKI YOUICHI ,  MITA TERUYOSHI

IPC: G06F13/00 ,  H04L1/24

Abstract: PURPOSE:To secure the function test with the single unit of the communication control unit by installing within the communication control unit the clock oscillator of the same frequency as the clock of the monitor device plus the delay memory featuring the equal time to the loop transmission delay time each. CONSTITUTION:When the single unit test mode is designated through the control panel, the clock sent from clock oscillation circuit 8 in the communication control unit is supplied to each part in place of the clock which is sent from the monitor device to repeater 2 via transmission line 1. And the data from control part 4 is sent to transmission part 5 via frame buffer memory 7. The data of the serial bits sent from part 5 is supplied to reception part 3 and then returned to part 4 again. As the delay time of memory 7 is equal to the loop delay time on the transmission line, the artifitial loop is formed within the communication control unit. Thus the data read out of memory 7 can be seen as if it were just on the transmission line. As a result, each block within the communication control unit features nearly the same operation as that of the normal operation, thus enabling the test with the single unit.

公开(公告)号：JPS55107362A

公开(公告)日：1980-08-18

申请号：JP1411979

申请日：1979-02-09

Applicant: FUJITSU LTD

Inventor： SUZUKI YOUICHI ,  KITANO YOSHIHIRO ,  MITA TERUYOSHI

IPC: H04L12/42

Abstract: PURPOSE:To enable to automatically cut off the power supply of other communication units at the same time, by transmitting the simultaneous power supply cut-off signal to the transmission line when the power supply for an arbitrary communication unit is cut off, and enabling other communication units to detect the signal. CONSTITUTION:When the power supply is cut off by closing the power off switch SW with an arbitrary communication unit Nl among a plurality of communication units, the simultaneous power supply cut off signal is delivered to the transmission line L from the cut-off signal generator 2 on the way of the power supply sequence. The signal is detected at the cut-off signal detection section 2' of other communication units to activate the relay RL4 and to cut off the power supply. In this case, since the time required for the delivery of the simultaneous power supply cut-off signal is very short, power supply cup-off can be made almost at the same time.

公开(公告)号：JPS54136237A

公开(公告)日：1979-10-23

申请号：JP4387378

申请日：1978-04-14

Applicant: FUJITSU LTD

Inventor： SAWADA TAKETOYO ,  HANADA AKIO ,  MITA TERUYOSHI ,  HOSHI FUMIO ,  SATOU MASAO

IPC: G11C11/406 ,  F02B75/02 ,  G06F12/00 ,  G06F12/06 ,  G06F13/00 ,  G11C7/22

Abstract: PURPOSE:To make adjustable the delivery period of the end timing signal, by controlling the system so that the intermediate timing signal can be longer for the element having longer access time, in the memory unit in mixture of memory elements in access time. CONSTITUTION:In accessing the high speed memory unit 3-A, when the memory unit usage request signal MRQ is fed from the operation unit 1, the start timing signal M1 is fed to the unit 1 with FF5. The sectioning of the memory units 3-A and 3-B is made with the address data, the intermediate timing signal M2 is produced with FF6 at the next cycle, the end timing signal M3 is produced with FF7 at the third cycle, and the unit 1 fetches the readout data. In accessing the low speed memory unit 3-B, FF12 is set with the signal MCYB under the usage of the memory unit B, signal M2 is stored, signal M3 is produced in 4 cycle, and the unit 1 fetches the readout data. The signal M2 is extended when the memory access request and the memory refresh request are in competition, until the refresh cycle is finished.

公开(公告)号：JPS54114994A

公开(公告)日：1979-09-07

申请号：JP2222078

申请日：1978-02-28

Applicant: FUJITSU LTD

Inventor： SAWADA TAKETOYO ,  HANADA AKIO ,  MITA TERUYOSHI ,  HOSHI FUMIO ,  SATOU MASAO

IPC: G09G3/20

Abstract: PURPOSE:To realize the input information display control system omitting the hold register in the serial transfer display system. CONSTITUTION:A plurality of selection circuits 2-0 to 2-7 which sequentially selects the information including the input information S00 to S77 from the input means of plurality corresponding to the matrix shaped display lamps P00 to P77, are provided and this output is connected to one of traversal or longitudinal line of the display lamp matrix with the serial transfer lines 3-0 to 3-7. Further, the counter 5 supplies the selective input signal to a plurality of selection circuits, and one of longitudinal row or traversal line of the display lamp matrix is made effective with the sequential display permissible control means 6 by means of the decoded outut of the counter 5.

公开(公告)号：JPS54114943A

公开(公告)日：1979-09-07

申请号：JP2221978

申请日：1978-02-28

Applicant: FUJITSU LTD

Inventor： SUZUKI YOUICHI ,  HANADA AKIO ,  MITA TERUYOSHI ,  HOSHI FUMIO ,  SATOU MASAO

IPC: G06F9/30 ,  G06F9/06

Abstract: PURPOSE:To satisfy the auxiliary decoder required on the printed board of each control section with the decoder having m inputs and also to satisfy it with the signal line of n-bit smaller than n-bit, in informing the instruction in n-bit to each printed board of control section. CONSTITUTION:The instruction in n-bit read out from the memory unit 1 is set to the instruction register 2, and simultaneously, it is converted into the instruction code of 6-bit with the encoder 8 at the instruction compression and conversion section 7. Further, this instruction code is fed to the auxiliary decoders 9-0 to 9-p of the printed boards 3-0 to 3-p of each control section. The printed boards 3-0 to 3-p discriminate the types of instruction read out from the unit 1 based on the said instruction code and output it to the control signal line 10. This signal line 10 turns on and off the gates for the work register 4, conventional register 5, and operation circuit 6, and performs operational processing by adding the content of the register 4-0 to one register of the registers 5(assuming A) and storing it to the register A, for example.