公开(公告)号：US12040776B2

公开(公告)日：2024-07-16

申请号：US16526633

申请日：2019-07-30

Applicant: Intel Corporation

Inventor： Telesphor Kamgaing ,  Aleksandar Aleksov ,  Feras Eid ,  Georgios Dogiamis ,  Johanna M. Swan

IPC: H03H9/05 ,  H01L23/00 ,  H01L23/538 ,  H01L25/00 ,  H01L25/18 ,  H03H9/58 ,  H10N30/87 ,  H10N30/88 ,  H10N39/00 ,  H01L23/498

CPC classification number: H03H9/0552 ,  H01L23/5385 ,  H01L24/16 ,  H01L25/18 ,  H01L25/50 ,  H03H9/58 ,  H10N30/875 ,  H10N30/883 ,  H10N39/00 ,  H01L23/49816 ,  H01L2224/16225 ,  H01L2924/19042

Abstract: Embodiments may relate to a radio frequency (RF) front-end module (FEM) that includes an acoustic wave resonator (AWR) die. The RF FEM may further include an active die coupled with the package substrate of the RF FEM. When the active die is coupled with the package substrate, the AWR die may be between the active die and the package substrate. Other embodiments may be described or claimed.

公开(公告)号：US20240222018A1

公开(公告)日：2024-07-04

申请号：US18147503

申请日：2022-12-28

Applicant: Intel Corporation

Inventor： Thomas Sounart ,  Henning Braunisch ,  Aleksandar Aleksov ,  Kristof Darmawikarta ,  Numair Ahmed ,  Darko Grujicic ,  Suddhasattwa Nad ,  Benjamin Duong ,  Marcel Wall ,  Shayan Kaviani

IPC: H01G4/01 ,  H01G4/30 ,  H01G4/33 ,  H01L21/48 ,  H01L23/538

CPC classification number: H01G4/01 ,  H01G4/306 ,  H01G4/33 ,  H01L21/4846 ,  H01L23/5386 ,  H01L28/87 ,  H01L28/92 ,  H01G4/008

Abstract: Substrate package-integrated oxide capacitors and related methods are disclosed herein. An example apparatus including a first layer and a thin film capacitor including a second layer on the first layer, the second layer defining a plurality of openings and a third layer disposed on the first layer and in the plurality of openings, the second layer and the third layer corresponding to electrodes of a capacitor and a fourth layer disposed between the first layer and the second layer, the third layer including an oxidized material, the third layer forming a dielectric of the capacitor.

公开(公告)号：US12002745B2

公开(公告)日：2024-06-04

申请号：US17544693

申请日：2021-12-07

Applicant: Intel Corporation

Inventor： Adel A. Elsherbini ,  Mathew J. Manusharow ,  Krishna Bharath ,  William J. Lambert ,  Robert L. Sankman ,  Aleksandar Aleksov ,  Brandon M. Rawlings ,  Feras Eid ,  Javier Soto Gonzalez ,  Meizi Jiao ,  Suddhasattwa Nad ,  Telesphor Kamgaing

IPC: H05K1/02 ,  H01F17/00 ,  H01F17/06 ,  H01F27/28 ,  H01F27/40 ,  H01F41/04 ,  H01G4/18 ,  H01G4/252 ,  H01G4/30 ,  H01G4/33 ,  H01L21/48 ,  H01L23/498 ,  H01L23/552 ,  H01L23/66 ,  H01L49/02

CPC classification number: H01L23/49838 ,  H01F17/0006 ,  H01F27/2804 ,  H01F27/40 ,  H01F41/041 ,  H01G4/33 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/66 ,  H01L28/00 ,  H01L28/10 ,  H01L28/60 ,  H01F2027/2809 ,  H01L2223/6661

Abstract: Embodiments of the invention include an electrical package and methods of forming the package. In one embodiment, a transformer may be formed in the electrical package. The transformer may include a first conductive loop that is formed over a first dielectric layer. A thin dielectric spacer material may be used to separate the first conductive loop from a second conductive loop that is formed in the package. Additional embodiments of the invention include forming a capacitor formed in the electrical package. For example, the capacitor may include a first capacitor plate that is formed over a first dielectric layer. A thin dielectric spacer material may be used to separate the first capacitor plate form a second capacitor plate that is formed in the package. The thin dielectric spacer material in the transformer and capacitor allow for increased coupling factors and capacitance density in electrical components.

公开(公告)号：US20240113005A1

公开(公告)日：2024-04-04

申请号：US17957751

申请日：2022-09-30

Applicant: Intel Corporation

Inventor： Jeremy Ecton ,  Aleksandar Aleksov ,  Hiroki Tanaka ,  Brandon Marin ,  Srinivas Pietambaram ,  Xavier Brun

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/00 ,  H01L23/13

CPC classification number: H01L23/49833 ,  H01L21/4803 ,  H01L21/481 ,  H01L21/4846 ,  H01L23/13 ,  H01L23/49894 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/80 ,  H01L24/16 ,  H01L2224/0346 ,  H01L2224/05647 ,  H01L2224/08145 ,  H01L2224/08225 ,  H01L2224/16146 ,  H01L2224/1624 ,  H01L2224/80201 ,  H01L2224/80379 ,  H01L2924/0665

Abstract: Microelectronic integrated circuit package structures include a first substrate coupled to a second substrate by a conductive interconnect structure and a dielectric material adjacent to the conductive interconnect structure. A cavity in a surface of the first substrate is adjacent to the conductive interconnect structure. A portion of the dielectric material is within the cavity.

公开(公告)号：US11908802B2

公开(公告)日：2024-02-20

申请号：US17842600

申请日：2022-06-16

Applicant: Intel Corporation

Inventor： Aleksandar Aleksov ,  Adel A. Elsherbini ,  Kristof Darmawikarta ,  Robert A. May ,  Sri Ranga Sai Boyapati

IPC: H01L23/538 ,  H01L25/18 ,  H01L25/065 ,  H01L21/48 ,  H01L23/00 ,  H01L23/31 ,  H01L25/00 ,  H01L23/498 ,  H01L21/56

CPC classification number: H01L23/5386 ,  H01L21/4853 ,  H01L21/4857 ,  H01L23/00 ,  H01L23/3121 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/49894 ,  H01L23/5383 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/73 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/18 ,  H01L25/50 ,  H01L21/561 ,  H01L21/568 ,  H01L23/5384 ,  H01L24/13 ,  H01L2224/1403 ,  H01L2224/14132 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/1703 ,  H01L2224/17181 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/95001 ,  H01L2224/97 ,  H01L2924/1517 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/381 ,  H01L2224/97 ,  H01L2224/81

Abstract: An apparatus is provided which comprises: a plurality of first conductive contacts having a first pitch spacing on a substrate surface, a plurality of second conductive contacts having a second pitch spacing on the substrate surface, and a plurality of conductive interconnects disposed within the substrate to couple a first grouping of the plurality of second conductive contacts associated with a first die site with a first grouping of the plurality of second conductive contacts associated with a second die site and to couple a second grouping of the plurality of second conductive contacts associated with the first die site with a second grouping of the plurality of second conductive contacts associated with the second die site, wherein the conductive interconnects to couple the first groupings are present in a layer of the substrate above the conductive interconnects to couple the second groupings. Other embodiments are also disclosed and claimed.

公开(公告)号：US11791528B2

公开(公告)日：2023-10-17

申请号：US17714957

申请日：2022-04-06

Applicant: Intel Corporation

Inventor： Adel A. Elsherbini ,  Mathew Manusharow ,  Krishna Bharath ,  Zhichao Zhang ,  Yidnekachew S. Mekonnen ,  Aleksandar Aleksov ,  Henning Braunisch ,  Feras Eid ,  Javier Soto

IPC: H01P3/08 ,  H01P3/02 ,  H05K1/02 ,  H01P3/06

CPC classification number: H01P3/082 ,  H01P3/02 ,  H01P3/026 ,  H01P3/06 ,  H01P3/08 ,  H01P3/085 ,  H01P3/088 ,  H05K1/0245

Abstract: Embodiments of the invention include a packaged device with transmission lines that have an extended thickness, and methods of making such device. According to an embodiment, the packaged device may include a first dielectric layer and a first transmission line formed over the first dielectric layer. Embodiments may then include a second dielectric layer formed over the transmission line and the first dielectric layer. According to an embodiment, a first line via may be formed through the second dielectric layer and electrically coupled to the first transmission line. In some embodiments, the first line via extends substantially along the length of the first transmission line.

公开(公告)号：US20230320021A1

公开(公告)日：2023-10-05

申请号：US18331474

申请日：2023-06-08

Applicant: Intel Corporation

Inventor： Telesphor Kamgaing ,  Johanna M. Swan ,  Georgios Dogiamis ,  Henning Braunisch ,  Adel A. Elsherbini ,  Aleksandar Aleksov ,  Richard Dischler

IPC: H05K7/14 ,  H05K1/02 ,  H01P5/12 ,  H01P3/16

CPC classification number: H05K7/1489 ,  H05K1/0243 ,  H01P5/12 ,  H01P3/16 ,  H05K2201/10356 ,  H01L24/16

Abstract: Embodiments may relate an electronic device that includes a first server blade and a second server blade coupled with a chassis. The first and second server blades may include respective microelectronic packages. The electronic device may further include a waveguide coupled to the first and second server blades such that their respective microelectronic packages are communicatively coupled by the waveguide. Other embodiments may be described or claimed.

公开(公告)号：US11728290B2

公开(公告)日：2023-08-15

申请号：US16394514

申请日：2019-04-25

Applicant: Intel Corporation

Inventor： Adel A. Elsherbini ,  Georgios Dogiamis ,  Johanna M. Swan ,  Aleksandar Aleksov ,  Telesphor Kamgaing ,  Henning Braunisch

IPC: H01L23/66 ,  H01L23/538 ,  H01L25/065 ,  H01L23/00 ,  H01L21/48 ,  H01L21/683 ,  H01L25/00

CPC classification number: H01L23/66 ,  H01L21/486 ,  H01L21/4857 ,  H01L21/6835 ,  H01L23/5386 ,  H01L24/16 ,  H01L25/0655 ,  H01L25/50 ,  H01L24/97 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2223/6616 ,  H01L2223/6627 ,  H01L2223/6683 ,  H01L2224/16227 ,  H01L2924/1423 ,  H01L2924/1903

Abstract: Embodiments may relate to a microelectronic package that includes a substrate signal path and a waveguide. The package may further include dies that are communicatively coupled with one another by the substrate signal path and the waveguide. The substrate signal path may carry a signal with a frequency that is different than the frequency of a signal that is to be carried by the waveguide. Other embodiments may be described or claimed.

公开(公告)号：US11728258B2

公开(公告)日：2023-08-15

申请号：US17536711

申请日：2021-11-29

Applicant: INTEL CORPORATION

Inventor： Aleksandar Aleksov ,  Veronica Strong ,  Kristof Darmawikarta ,  Arnab Sarkar

IPC: H05K1/02 ,  H05K1/03 ,  H05K1/09 ,  H05K3/02 ,  H05K3/06 ,  H05K3/07 ,  H05K3/10 ,  H01L21/00 ,  H01L21/48 ,  H01L23/00 ,  H01L23/48 ,  H01L23/498 ,  H05K1/11 ,  H05K3/18

CPC classification number: H01L23/49827 ,  H01L21/486 ,  H01L23/49866 ,  H05K1/113 ,  H05K3/184 ,  H05K2201/0379 ,  H05K2203/0565

Abstract: A package substrate, comprising a package comprising a substrate, the substrate comprising a dielectric layer, a via extending to a top surface of the dielectric layer; and a bond pad stack having a central axis and extending laterally from the via over the first layer. The bond pad stack is structurally integral with the via, wherein the bond pad stack comprises a first layer comprising a first metal disposed on the top of the via and extends laterally from the top of the via over the top surface of the dielectric layer adjacent to the via. The first layer is bonded to the top of the via and the dielectric layer, and a second layer is disposed over the first layer. A third layer is disposed over the second layer. The second layer comprises a second metal and the third layer comprises a third metal. The second layer and the third layer are electrically coupled to the via.

公开(公告)号：US11721650B2

公开(公告)日：2023-08-08

申请号：US16437930

申请日：2019-06-11

Applicant: Intel Corporation

Inventor： Brandon C. Marin ,  Aleksandar Aleksov ,  Georgios Dogiamis ,  Jeremy D. Ecton ,  Suddhasattwa Nad ,  Mohammad Mamunur Rahman

IPC: H01L23/66 ,  H01L23/498 ,  H01L21/48 ,  H01P3/08 ,  H01P11/00 ,  H01P3/06

CPC classification number: H01L23/66 ,  H01L21/481 ,  H01L21/4846 ,  H01L23/49838 ,  H01P3/06 ,  H01P3/08 ,  H01P3/088 ,  H01P11/003 ,  H01P11/005 ,  H01L2223/6627

Abstract: Embodiments include semiconductor packages and method of forming the semiconductor packages. A semiconductor package includes first waveguides over a package substrate. The first waveguides include first angled conductive layers, first transmission lines, and first cavities. The semiconductor package also includes a first dielectric over the first waveguides and package substrate, second waveguides over the first dielectric and first waveguides, and a second dielectric over the second waveguides and first dielectric. The second waveguides include second angled conductive layers, second transmission lines, and second cavities. The first angled conductive layers are positioned over the first transmission lines and package substrate having a first pattern of first triangular structures. The second angled conductive layers are positioned over the second transmission lines and first dielectric having a second pattern of second triangular structures, where the second pattern is shaped as a coaxial interconnects enclosed with second triangular structures and portions of first dielectric.