公开(公告)号：WO1996002916A1

公开(公告)日：1996-02-01

申请号：PCT/US1995007745

申请日：1995-06-16

Applicant: INTEL CORPORATION

Inventor： INTEL CORPORATION ,  ROSEN, Eitan ,  MILSTAIN, Yakov

IPC: G11C13/00

CPC classification number: G11C29/50016 ,  G11C11/41 ,  G11C29/50

Abstract: A memory circuit (20) is disclosed with stress circuitry for detecting data retention defects in the memory cells. The memory circuit (20) comprises a memory cell array (22) coupled to bit lines, an access circuit (24) coupled to access the memory cells, and a discharge circuit coupled to stress the memory cells.

Abstract translation: 公开了一种用于检测存储器单元中的数据保持缺陷的应力电路的存储器电路（20）。 存储器电路（20）包括耦合到位线的存储单元阵列（22），耦合到存取单元的存取电路（24），以及耦合以压缩存储单元的放电电路。

公开(公告)号：WO1996000946A1

公开(公告)日：1996-01-11

申请号：PCT/US1995008072

申请日：1995-06-26

Applicant: INTEL CORPORATION

Inventor： INTEL CORPORATION ,  ADAMS, Robert

IPC: G06F17/30

CPC classification number: G06F17/30017 ,  Y10S707/99945 ,  Y10S707/99948

Abstract: A multimedia architecture for pre-fetching data from a server provides limited-memory client machines with the ability to take advantage of a large remote database with relatively quick response time. A compiler program analyzes a given script to determine what data is needed by the current script and what potential scripts might be addressed from the current script and what server-stored data those scripts would need. That data is pre-fetched from the server upon commands from the compiler program in order to be quickly available for display at the client machine if requested by a user.

Abstract translation: 用于从服务器预取数据的多媒体架构提供了有限的内存客户端机器，能够以较快的响应时间利用大型远程数据库。 编译器程序分析给定的脚本以确定当前脚本需要哪些数据，以及可能从当前脚本中解决哪些潜在脚本以及这些脚本需要哪些服务器存储的数据。 根据来自编译器程序的命令，从服务器预取数据，以便在用户请求时可快速地在客户机上显示。

公开(公告)号：WO1995033232A1

公开(公告)日：1995-12-07

申请号：PCT/US1995005588

申请日：1995-05-04

Applicant: INTEL CORPORATION

Inventor： INTEL CORPORATION ,  TEDROW, Kerry ,  KEENEY, Stephen ,  FAZIO, Albert ,  ATWOOD, Gregory ,  JAVANIFARD, Johnny ,  WOJCIECHOWSKI, Kenneth

IPC: G05F01/10

CPC classification number: G11C11/5621 ,  G05F1/465 ,  G11C5/147 ,  G11C16/30

Abstract: A voltage regulation circuit (45) that includes a sample and hold circuit (501) for sampling an input voltage (Vin). The sample and hold circuit (501) includes a capacitor (C1, 515) that holds the reference voltage. The voltage regulation circuit (45) also includes a regulator circuit (503) coupled to the capacitor (C1) of the sample and hold circuit (501). The regulator circuit (503) outputs an output voltage using the reference voltage supplied by the capacitor (C1). The voltage regulation circuit (45) may be used to provide a high precision programming voltage for programming memory cells having two or more analog states.

Abstract translation: 一种电压调节电路（45），包括用于对输入电压（Vin）进行采样的取样和保持电路（501）。 采样保持电路（501）包括保持参考电压的电容器（C1,515）。 电压调节电路（45）还包括耦合到采样和保持电路（501）的电容器（C1）的调节器电路（503）。 调节器电路（503）使用由电容器（C1）提供的参考电压输出输出电压。 电压调节电路（45）可用于为具有两个或多个模拟状态的存储器单元的编程提供高精度编程电压。

公开(公告)号：WO1995032474A1

公开(公告)日：1995-11-30

申请号：PCT/US1995006089

申请日：1995-05-16

Applicant: INTEL CORPORATION

Inventor： INTEL CORPORATION ,  BELL, D., Michael ,  GONZALES, Mark, A. ,  MEREDITH, Susan, S.

IPC: G06F13/00

CPC classification number: G06F13/4027

Abstract: A bus bridge (400) between two buses includes two request queues: outbound (420) and inbound (430). Requests originating on the first bus (401) which target a destination on the second bus (402) are placed into the outbound queue (420). If the request can be deferred, decoding circuitry (415) within the bridge (400) issues a deferred response to the originating agent, indicating the request will be serviced later. Bus control circuitry (425) removes requests from the outbound queue (420) and executes them on the second bus (402). When bus control circuitry (425) receives a response from the destination agent in response to this execution, it either returns the response to the originating agent immediately or after passing it through the inbound queue (430). Both queues (420, 430) have associated data buffers (520, 530) for transferring data between the two buses (401, 402). Requests are handled similarly in the opposite direction, with the request originating on the second bus (402) for execution on the first bus (401).

Abstract translation: 两条总线之间的总线桥（400）包括两个请求队列：出站（420）和入站（430）。 发起在第二总线（402）上的目的地的第一总线（401）上的请求被放置到出站队列（420）中。 如果请求可以延迟，桥接器（400）内的解码电路（415）向发起方发出延迟响应，指示稍后将对该请求进行服务。 总线控制电路（425）从出站队列（420）中移除请求并在第二总线（402）上执行它们。 当总线控制电路（425）响应于该执行接收到来自目的地代理的响应时，它或者立即或者在通过入站队列（430）通过之后返回到始发代理的响应。 两个队列（420,430）具有用于在两个总线（401,402）之间传送数据的相关联的数据缓冲器（520,530）。 请求在相反的方向上处理相似，请求始发于第二总线（402）以便在第一总线（401）上执行。

公开(公告)号：WO1995032460A1

公开(公告)日：1995-11-30

申请号：PCT/US1995006515

申请日：1995-05-23

Applicant: INTEL CORPORATION

Inventor： INTEL CORPORATION ,  GILLESPIE, Byron, R. ,  GARBUS, Elliot, D. ,  KAHN, Mitchell, A. ,  JOHNSON, Thomas, M. ,  O'CONNOR, Dennis, M. ,  HEEB, Jay, S.

IPC: G06F03/00

CPC classification number: G06F12/1441

Abstract: The system and method described provide for the detection and protection of memory accesses without the overhead typically incurred by memory management units. The processor includes a guarded memory unit, which monitors memory accesses to be performed by monitoring transmissions across the memory bus (510, 520, 530, 540). The guarded memory unit includes a plurality of registers which identify memory addresses (555, 565, 575, 585) and modes (550, 560, 570, 580) which can cause a memory protection or detection violation to occur. If a memory protection violation occurs, a cancel signal is issued to cancel the memory operation prior to completion in order to protect the memory from unauthorized accesses (350). If a memory violation is detected, the memory operation is permitted to complete and a fault signal is issued to the processor to identify that a memory violation has been detected. As the structure of the protection mechanism does not require separate cycles in the processor, and simply monitors the memory bus for memory accesses, memory protection and detection can be performed with no additional overhead at the processor.

Abstract translation: 所描述的系统和方法提供了对存储器访问的检测和保护，而不需要由存储器管理单元引起的开销。 该处理器包括一个被保护的存储器单元，该存储器单元通过监控跨存储器总线（510,520,530,540）的传输来监视要执行的存储器访问。 保护存储单元包括多个寄存器，其识别可能导致存储器保护或检测违规发生的存储器地址（555,556,575,585）和模式（550,560,570,580）。 如果发生存储器保护违规，则在完成之前发出取消信号以取消存储器操作，以保护存储器免受未经授权的访问（350）。 如果检测到存储器冲突，则允许存储器操作完成，并且向处理器发出故障信号以识别已经检测到存储器违规。 由于保护机构的结构在处理器中不需要单独的周期，并且简单地监视存储器总线以进行存储器访问，所以可以在处理器没有额外的开销的情况下执行存储器保护和检测。

公开(公告)号：WO1995030946A1

公开(公告)日：1995-11-16

申请号：PCT/US1995005723

申请日：1995-05-09

Applicant: INTEL CORPORATION

Inventor： INTEL CORPORATION ,  SINGH, Gurbir ,  RHODEHAMEL, Michael, W.

IPC: G06F01/04

CPC classification number: H03K5/26 ,  G06F13/405 ,  H03K5/135 ,  H03K5/153 ,  H03L7/183 ,  H04L7/0012

Abstract: An apparatus (7) for synchronously transmitting data between devices operating at different frequencies that have a P/Q integer ratio relationship. The apparatus allows one or more device(s) operating at a high frequency (16) to synchronously exchange data with one or more device(s) operating at a low frequency (18). The frequency relationship is: low frequency = (P/Q) X high frequency; where P and Q represent integer values, P is less that Q, and Q is not necessarily an integer multiple of P. A clock generator (10) generates one or both of the frequency clocks according to the P/Q frequency ratio. The interface controller (12) receives the high (low) frequency clock and the P and Q values as inputs and generates a high-to low (low-to high) data transfer signal. Data transfer signals indicate safe times (a high frequency clock period with stable transfer data and the receiver ready) or windows for transferring data across frequency boundaries (14).

Abstract translation: 一种用于在具有P / Q整数比关系的不同频率工作的设备之间同步发送数据的装置（7）。 该装置允许以高频（16）操作的一个或多个设备与在低频（18）下操作的一个或多个设备同步地交换数据。 频率关系为：低频=（P / Q）X高频; 其中P和Q表示整数值，P小于Q，Q不一定是P的整数倍。时钟发生器（10）根据P / Q频率比产生一个或两个频率时钟。 接口控制器（12）接收高（低）频率时钟和P和Q值作为输入，并产生高到低（从低到高）数据传输信号。 数据传输信号表示安全时间（具有稳定传输数据和接收器就绪的高频时钟周期）或用于在频率边界传输数据的窗口（14）。

公开(公告)号：WO1995027249A1

公开(公告)日：1995-10-12

申请号：PCT/US1995004109

申请日：1995-04-03

Applicant: INTEL CORPORATION

Inventor： INTEL CORPORATION ,  TOUBOUL, Shlomo

IPC: G06F11/00

CPC classification number: G06F11/0709 ,  G06F11/0715 ,  G06F11/0748 ,  G06F11/0757 ,  G06F11/2294 ,  G06F11/2736 ,  G06F11/3006 ,  G06F11/302 ,  G06F11/3093 ,  G06F11/327 ,  G06F11/3466 ,  G06F11/3495 ,  G06F2201/86 ,  G06F2201/865 ,  H04L41/0213 ,  H04L41/046 ,  H04L41/06 ,  H04L41/0654 ,  H04L41/20 ,  H04L43/00 ,  H04L43/0817

Abstract: A system for monitoring and controlling at least one program capable of being executed on any one of at least two workstations in a network. The network includes at least one agent module (14) resident on each of the at least two workstations (10) and a management console (1) connected to each of the at least two workstations (10). The system includes modules for identifying an event occuring with respect to a program executing on one of the at least two workstations (10), modules for sending an alert to the management console (1) which identifies the event, memory for storing a plurality of triggers (8), each of the triggers (8) adapted to cause an action to be taken within the network, memory for storing at least one procedure (5) comprising at least one of the plurality of triggers (8), and modules for sending at least one of the procedures (5) from the management console (1) to the agent module (14) resident on the one of the at least two workstations (10) in response to receipt of the alert. A method is also provided for monitoring and controlling programs capable of being executed on any of at least two workstations (10) in a network.

Abstract translation: 一种用于监视和控制能够在网络中的至少两个工作站中的任何一个上执行的至少一个程序的系统。 所述网络包括驻留在所述至少两个工作站（10）中的每一个上的至少一个代理模块（14）和连接到所述至少两个工作站（10）中的每一个的管理控制台（1）。 所述系统包括用于识别关于在所述至少两个工作站（10）中的一个上执行的程序发生的事件的模块，用于向标识所述事件的管理控制台（1）发送警报的模块，用于存储多个 触发器（8），每个触发器（8）适于使得在网络内采取动作，用于存储至少一个包括多个触发器（8）中的至少一个触发器（8）的过程（5）的存储器，以及用于 响应于接收到警报，将至少一个程序（5）从管理控制台（1）发送到驻留在至少两个工作站（10）中的一个上的代理模块（14）。 还提供了一种用于监视和控制能够在网络中的至少两个工作站（10）中的任何一个上执行的程序的方法。

公开(公告)号：WO1994024629A1

公开(公告)日：1994-10-27

申请号：PCT/US1994003960

申请日：1994-04-12

Applicant: INTEL CORPORATION

Inventor： INTEL CORPORATION ,  AHIMOVIC, Peter, J. ,  MANEPALLY, Narayan

IPC: G06F15/21

CPC classification number: G06F9/543 ,  G06Q10/10 ,  H04M3/567 ,  H04M7/006 ,  H04N7/147

Abstract: A system for computer supported collaboration is provided wherein two applications, having individual input devices, are coupled to a network which transmits application data between the two applications. Each application is capable of processing its own application data and the application data of the application at the remote end of the network simultaneously.

Abstract translation: 提供了一种用于计算机支持协作的系统，其中具有各个输入设备的两个应用被耦合到在两个应用之间传送应用数据的网络。 每个应用程序能够同时在网络的远端处理自己的应用程序数据和应用程序的应用程序数据。

公开(公告)号：WO1994014198A1

公开(公告)日：1994-06-23

申请号：PCT/US1993011116

申请日：1993-11-16

Applicant: INTEL CORPORATION

Inventor： INTEL CORPORATION ,  CHAU, Robert, S. ,  FRASER, David, B. ,  CADIEN, Kenneth, C. ,  RAGHAVAN, Gopal ,  YAU, Leopoldo, D.

IPC: H01L29/76

CPC classification number: H01L29/6659 ,  H01L21/2807 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/28097 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/4975 ,  H01L29/665 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A novel, reliable, high performance MOS transistor (300) with a composite gate electrode which is compatible with standard CMOS fabrication processes. The composite gate electrode comprises a polysilicon layer (302) formed on a highly conductive layer (304). The composite gate electrode is formed on a gate insulating layer (301) which is formed on a silicon substrate (308). A pair of source/drain regions (310a, 310b) are formed in the substrate and are self-aligned to the outside edges of the composite gate electrode.

Abstract translation: 一种具有与标准CMOS制造工艺兼容的复合栅电极的新颖可靠的高性能MOS晶体管（300）。 复合栅电极包括形成在高导电层（304）上的多晶硅层（302）。 复合栅电极形成在形成在硅衬底（308）上的栅极绝缘层（301）上。 一对源极/漏极区（310a，310b）形成在衬底中并且与复合栅电极的外边缘自对准。

公开(公告)号：WO1993021623A1

公开(公告)日：1993-10-28

申请号：PCT/US1993002773

申请日：1993-03-24

Applicant: INTEL CORPORATION

Inventor： INTEL CORPORATION ,  LIPPINCOTT, Louis, A.

IPC: G09G01/16

CPC classification number: G09G5/397 ,  G09G5/06 ,  G09G5/363 ,  G09G2340/125 ,  H04N5/44504

Abstract: An apparatus for processing visual data is comprised of a first storage means for storing a first bit plane of visual data in a first format. A graphics controller is coupled to the first storage means by a data bus and through a storage bus. Means for receiving a second storage means for storing a second bit plane of visual data in a second format different from the first format is also provided. The receiving means is adapted to couple a second storage means to the graphics controller by a data bus and through a storage bus. Means for forming a merged pixel stream from visual data stored on the first and second storage means are also included. Means, coupled to the graphics controller, are provided for displaying the merged pixel stream. In a further embodiment, an apparatus for processing visual data is comprised of a first storage means for storing a first bit plane of visual data in a first format. A graphics controller is coupled to the first storage means by a data bus and through a storage bus. A second storage means coupled to the graphics controller by a data bus and through a storage bus is provided for storing a second bit plane of visual data in a second format different from the first format. Means for forming a merged pixel stream from visual data stored on the first and second storage means are also included. Means, coupled to the graphics controller, are provided for displaying the merged pixel stream.

Abstract translation: 一种用于处理视觉数据的装置包括用于以第一格式存储视觉数据的第一位平面的第一存储装置。 图形控制器通过数据总线和存储总线耦合到第一存储装置。 还提供了用于接收用于以不同于第一格式的第二格式存储可视数据的第二位平面的第二存储装置的装置。 接收装置适于通过数据总线和存储总线将第二存储装置耦合到图形控制器。 还包括用于从存储在第一和第二存储装置上的可视数据形成合并像素流的装置。 耦合到图形控制器的装置被提供用于显示合并的像素流。 在另一个实施例中，一种用于处理视觉数据的装置包括用于以第一格式存储视觉数据的第一位平面的第一存储装置。 图形控制器通过数据总线和存储总线耦合到第一存储装置。 提供了通过数据总线和通过存储总线耦合到图形控制器的第二存储装置，用于以不同于第一格式的第二格式存储可视数据的第二位平面。 还包括用于从存储在第一和第二存储装置上的可视数据形成合并像素流的装置。 耦合到图形控制器的装置被提供用于显示合并的像素流。