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    HIGH PRECISION VOLTAGE REGULATION CIRCUIT FOR PROGRAMMING MULTILEVEL FLASH MEMORY
    1.
    发明申请
    HIGH PRECISION VOLTAGE REGULATION CIRCUIT FOR PROGRAMMING MULTILEVEL FLASH MEMORY 审中-公开
    用于编程多级闪存的高精度电压调节电路

    公开(公告)号：WO1995033232A1

    公开(公告)日：1995-12-07

    申请号：PCT/US1995005588

    申请日：1995-05-04

    Applicant: INTEL CORPORATION

    Inventor： INTEL CORPORATION ,  TEDROW, Kerry ,  KEENEY, Stephen ,  FAZIO, Albert ,  ATWOOD, Gregory ,  JAVANIFARD, Johnny ,  WOJCIECHOWSKI, Kenneth

    IPC: G05F01/10

    CPC classification number: G11C11/5621 ,  G05F1/465 ,  G11C5/147 ,  G11C16/30

    Abstract: A voltage regulation circuit (45) that includes a sample and hold circuit (501) for sampling an input voltage (Vin). The sample and hold circuit (501) includes a capacitor (C1, 515) that holds the reference voltage. The voltage regulation circuit (45) also includes a regulator circuit (503) coupled to the capacitor (C1) of the sample and hold circuit (501). The regulator circuit (503) outputs an output voltage using the reference voltage supplied by the capacitor (C1). The voltage regulation circuit (45) may be used to provide a high precision programming voltage for programming memory cells having two or more analog states.

    Abstract translation: 一种电压调节电路（45），包括用于对输入电压（Vin）进行采样的取样和保持电路（501）。 采样保持电路（501）包括保持参考电压的电容器（C1,515）。 电压调节电路（45）还包括耦合到采样和保持电路（501）的电容器（C1）的调节器电路（503）。 调节器电路（503）使用由电容器（C1）提供的参考电压输出输出电压。 电压调节电路（45）可用于为具有两个或多个模拟状态的存储器单元的编程提供高精度编程电压。

    DATA ERROR RECOVERY IN NON-VOLATILE MEMORY
    2.
    发明申请
    DATA ERROR RECOVERY IN NON-VOLATILE MEMORY 审中-公开
    非易失性存储器中的数据错误恢复

    公开(公告)号：WO2010080257A2

    公开(公告)日：2010-07-15

    申请号：PCT/US2009/066612

    申请日：2009-12-03

    Applicant: INTEL CORPORATION ,  COULSON, Richard ,  FAZIO, Albert ,  KHAN, Jawad

    Inventor： COULSON, Richard ,  FAZIO, Albert ,  KHAN, Jawad

    IPC: G06F11/08 ,  G06F12/16

    CPC classification number: G11C16/3404 ,  G06F11/1068 ,  G11C29/52 ,  G11C2029/0411

    Abstract: When an error correction code (ECC) unit finds uncorrectable errors in a solid state non-volatile memory device, a process may be used in an attempt to locate and correct the errors. This process may first identify 'low confidence' memory cells that are likely to contain errors, and then determine what data is more likely to be correct in those cells, based on various criteria. The new data may then be checked with the ECC unit to verify that it is sufficiently correct for the ECC unit to correct any remaining errors.

    Abstract translation: 当纠错码（ECC）单元在固态非易失性存储设备中发现不可纠正的错误时，可以使用过程来尝试定位和纠正错误。 该过程可以首先识别可能包含错误的“低置信度”存储器单元，然后基于各种标准确定哪些数据在这些单元中更可能是正确的。 然后可以用ECC单元检查新的数据，以验证它对于ECC单元是否足够正确以纠正任何剩余的错误。

    METHOD, APPARATUS AND SYSTEM TO DETERMINE ACCESS INFORMATION FOR A PHASE CHANGE MEMORY
    4.
    发明申请
    METHOD, APPARATUS AND SYSTEM TO DETERMINE ACCESS INFORMATION FOR A PHASE CHANGE MEMORY 审中-公开
    方法，装置和系统来确定相位变化记忆的访问信息

    公开(公告)号：WO2012040680A1

    公开(公告)日：2012-03-29

    申请号：PCT/US2011/053171

    申请日：2011-09-24

    Applicant: INTEL CORPORATION ,  KAU, DerChang ,  FAZIO, Albert

    Inventor： KAU, DerChang ,  FAZIO, Albert

    IPC: G11C13/02 ,  G11C16/06

    CPC classification number: G11C13/0004 ,  G11C13/004 ,  G11C13/0061 ,  G11C2013/0057

    Abstract: Techniques for determining access information describing an accessing of a phase change memory (PCM) device. In an embodiment, an initial read time for a PCM cell is determined based on a final read time for the PCM cell, set threshold voltage information and a reset threshold voltage drift, wherein the final read time and the initial read time define a time window for reading the PCM cell. In another embodiment, a time window extension is determined based on a reset threshold voltage drift.

    Abstract translation: 用于确定描述相变存储器（PCM）设备的访问的访问信息的技术。 在一个实施例中，基于PCM单元的最终读取时间，设置阈值电压信息和复位阈值电压漂移来确定PCM单元的初始读取时间，其中最终读取时间和初始读取时间限定时间窗口 用于读取PCM单元。 在另一个实施例中，基于复位阈值电压漂移来确定时间窗延伸。

    MEMS PROBE BASED MEMORY
    5.
    发明申请
    MEMS PROBE BASED MEMORY 审中-公开
    基于MEMS探头的存储器

    公开(公告)号：WO2006071834A2

    公开(公告)日：2006-07-06

    申请号：PCT/US2005/046990

    申请日：2005-12-21

    Applicant: INTEL CORPORATION ,  LAI, Stefan ,  FAZIO, Albert ,  RAO, Valluri ,  BROWN, Mike ,  MURALI, Krisnamurthy

    Inventor： LAI, Stefan ,  FAZIO, Albert ,  RAO, Valluri ,  BROWN, Mike ,  MURALI, Krisnamurthy

    IPC: G11B9/00

    CPC classification number: G11C23/00 ,  B82Y10/00 ,  G11B9/1436 ,  G11B9/149 ,  G11C13/0004

    Abstract: In accordance with one embodiment of the invention, a memory device may include a memory layer and a MEMS layer. The memory layer may include an integrated circuit with a multiplexer and optionally a memory controller and a storage medium disposed on the integrated circuit where the storage medium includes chalcogenide islands as storage elements. The MEMS layer may include a movable MEMS platform having probes to connect selected chalcogenide islands via positioning of the MEMS platform. A high voltage source disposed external to the memory layer and the MEMS layer may provide a high voltage to a stator electrode on the memory layer and to a rotor electrode on the MEMS platform to control movement of the MEMS platform with respect to the storage medium. The memory device may be utilized in portable electronic devices such as media players and cellular telephones to provide a nonvolatile storage of information.

    Abstract translation: 根据本发明的一个实施例，存储器件可以包括存储器层和MEMS层。 存储器层可以包括具有多路复用器的集成电路以及可选地存储器控制器和设置在集成电路上的存储介质，其中存储介质包括作为存储元件的硫族化物岛。 MEMS层可以包括具有探针的可移动MEMS平台，以通过MEMS平台的定位连接选定的硫族化物岛。 设置在存储层和MEMS层外部的高电压源可以向存储层上的定子电极和MEMS平台上的转子电极提供高电压，以控制MEMS平台相对于存储介质的移动。 存储器装置可用于诸如媒体播放器和蜂窝电话之类的便携式电子装置中以提供信息的非易失性存储。

    SCALABLE BANDWIDTH NON-VOLATILE MEMORY
    8.
    发明申请
    SCALABLE BANDWIDTH NON-VOLATILE MEMORY 审中-公开
    可扩展的带宽非易失性存储器

    公开(公告)号：WO2018063728A1

    公开(公告)日：2018-04-05

    申请号：PCT/US2017/049502

    申请日：2017-08-30

    Applicant: INTEL CORPORATION

    Inventor： SUNDARAM, Rajesh ,  FAZIO, Albert ,  KAU, Derchang ,  QAWAMI, Shekoufeh

    IPC: G06F13/16 ,  G11C13/00

    Abstract: Cross point memory architectures, devices, systems, and methods are disclosed and described, and can include a cross point memory core subsystem having increased bandwidth that is scalable. The memory core can include a plurality of independently operating partitions, each comprising a plurality of cross point memory arrays.

    Abstract translation: 公开并描述了交叉点存储器体系结构，设备，系统和方法，并且可以包括具有可扩展的增加的带宽的交叉点存储器核心子系统。 存储器核心可以包括多个独立操作的分区，每个分区包括多个交叉点存储器阵列。

    A FLASH MEMORY DEVICE HAVING A PAGE MODE OF OPERATION
    9.
    发明申请
    A FLASH MEMORY DEVICE HAVING A PAGE MODE OF OPERATION 审中-公开
    具有页面操作模式的闪存存储器件

    公开(公告)号：WO1998008226A1

    公开(公告)日：1998-02-26

    申请号：PCT/US1997011020

    申请日：1997-06-24

    Applicant: INTEL CORPORATION

    Inventor： INTEL CORPORATION ,  FAZIO, Albert

    IPC: G11C16/06

    CPC classification number: G11C16/26 ,  G11C7/00 ,  G11C7/12

    Abstract: A method for determining data stored by a memory cell (35). The memory cell (35) has a select gate coupled to a wordline (40), a first electrode coupled to a bitline (45), and a second electrode coupled to a conductor. The method comprises floating the bitline (45); applying a first voltage (Vg) to the wordline (40); applying a second voltage (Vs) to the conductor such that the bitline is set to a third voltage (Vg-Vt) that is equal to the first voltage (Vg) minus a threshold voltage (Vt) of the memory cell (35); and sensing the third voltage (Vg-Vt) to determine the data stored by the memory cell (35).

    Abstract translation: 一种用于确定由存储单元（35）存储的数据的方法。 存储单元（35）具有耦合到字线（40）的选择栅极，耦合到位线（45）的第一电极和耦合到导体的第二电极。 该方法包括使位线（45）浮动; 向所述字线（40）施加第一电压（Vg）; 向所述导体施加第二电压（Vs），使得所述位线被设定为等于所述第一电压（Vg）减去所述存储单元（35）的阈值电压（Vt）的第三电压（Vg-Vt）; 并感测第三电压（Vg-Vt）以确定由存储单元（35）存储的数据。

    SENSING STATE OF A MEMORY BY VARIABLE GATE VOLTAGE
    10.
    发明申请
    SENSING STATE OF A MEMORY BY VARIABLE GATE VOLTAGE 审中-公开
    通过可变门电压感知状态

    公开(公告)号：WO1996010256A1

    公开(公告)日：1996-04-04

    申请号：PCT/US1995012082

    申请日：1995-09-22

    Applicant: INTEL CORPORATION

    Inventor： INTEL CORPORATION ,  FAZIO, Albert ,  ATWOOD, Gregory, E. ,  BAUER, Mark, E.

    IPC: G11C07/00

    CPC classification number: G11C11/5621 ,  G11C7/16 ,  G11C11/5642 ,  G11C27/005 ,  G11C2211/5634 ,  G11C2211/5642 ,  G11C2211/5644

    Abstract: A method and apparatus for sensing the state of floating gate memory cells in a memory array (214). Because of its stability and accuracy, the sensing apparatus (220) may be used for sensing the state of multi-bit floating gate memory cells. The state of memory cell is sensed by applying a variable gate voltage to the top gate of the floating gate memory cell and comparing the cell current to a fixed reference current. A circuit detects when the cell current is equal to the reference current. When the currents are equal, the value of the variable gate voltage indicates the state of the memory cell. For one embodiment, an analog-to-digital converter (210) converts the variable gate voltage to a digital value that is latched when the currents are equal. The latched digital value indicates the state of the memory cell. For this embodiment, a ramp voltage or other suitable variable voltage may be used as the variable gate voltage. For another embodiment, a digital-to-analog converter is used to generate the variable gate voltage.

    Abstract translation: 一种用于感测存储器阵列（214）中的浮动栅极存储器单元的状态的方法和装置。 由于其稳定性和精度，感测装置（220）可以用于感测多位浮动栅极存储单元的状态。 通过将可变栅极电压施加到浮动栅极存储器单元的顶部栅极并将单元电流与固定参考电流进行比较来感测存储单元的状态。 电路检测电池电流何时等于参考电流。 当电流相等时，可变栅极电压的值表示存储单元的状态。 对于一个实施例，模数转换器（210）将可变栅极电压转换为当电流相等时被锁存的数字值。 锁存的数字值表示存储单元的状态。 对于该实施例，可以使用斜坡电压或其它合适的可变电压作为可变栅极电压。 对于另一个实施例，使用数模转换器来产生可变栅极电压。

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