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    GENERATING AUGMENTED DATA TO TRAIN MACHINE LEARNING MODELS TO PRESERVE PHYSICAL TRENDS
    135.
    发明申请
    GENERATING AUGMENTED DATA TO TRAIN MACHINE LEARNING MODELS TO PRESERVE PHYSICAL TRENDS 审中-公开

    公开(公告)号：WO2023084063A1

    公开(公告)日：2023-05-19

    申请号：PCT/EP2022/081686

    申请日：2022-11-12

    Applicant: ASML NETHERLANDS B.V.

    Inventor： REN, Jiaxing ,  FAN, Yongfa ,  CHEN, Yi-Yin ,  ZHANG, Chenji ,  ZHENG, Leiwu

    IPC: G03F7/20

    Abstract: Machine learning models can be trained to predict imaging characteristics with respect to variation in a pattern on a wafer resulting from a patterning process. However, due to low pattern coverage provided by limited wafer data used for training, machine learning models tend to overfit, and predictions from the machine learning models deviate from physical trends that characterize the pattern on the wafer and/or the patterning process with respect to the pattern variation. To enhance pattern coverage, training data is augmented with pattern data that conforms to a certain expected physical trend, and applies to new patterns not covered by previously measured wafer data.

    UTILITY STAGE FOR PHOTOLITHOGRAPHIC APPARATUS AND METHOD
    136.
    发明申请
    UTILITY STAGE FOR PHOTOLITHOGRAPHIC APPARATUS AND METHOD 审中-公开

    公开(公告)号：WO2023083582A1

    公开(公告)日：2023-05-19

    申请号：PCT/EP2022/079327

    申请日：2022-10-20

    Applicant: ASML NETHERLANDS B.V.

    Inventor： LEVY, Keane, Michael ,  NG, Amy

    IPC: G03F7/20

    Abstract: Disclosed is an apparatus for and method of using an in-system utility stage to provide service functions for wafer tables and other components in the photolithographic system in which the utility stage can access multiple tools without any need to open an enclosure containing the utility stage and the wafer tables and other components thus increasing throughput and decreasing downtime.

    PATTERN MATCHING METHOD
    139.
    发明申请
    PATTERN MATCHING METHOD 审中-公开

    公开(公告)号：WO2023066657A1

    公开(公告)日：2023-04-27

    申请号：PCT/EP2022/077591

    申请日：2022-10-04

    Applicant: ASML NETHERLANDS B.V.

    Inventor： FANG, Tsung-Pao ,  LIN, Wei-Chou ,  LIN, Hao ,  SONG, Chao

    IPC: G03F1/36 ,  G03F1/70 ,  G03F7/20

    Abstract: Described herein is a method for grouping patterns associated with one or more design layouts of a semiconductor. The method involves obtaining a set of patterns (e.g., from one or more design layouts), where a pattern of the set of patterns includes a non-intersected feature portion (e.g., parallel bars) within a bounding box of the pattern. A non-intersected feature portion of a pattern is encoded to a pattern representation having elements, where each element has a first component indicating a type of an individual non-intersected feature portion, and a second component indicating a width of the individual non-intersected feature portion projected along a designated edge of an area enclosing the pattern. The set of patterns are grouped into one or more groups by comparing the pattern representations associated the set of patterns.

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