公开(公告)号：US09919522B2

公开(公告)日：2018-03-20

申请号：US15258041

申请日：2016-09-07

Applicant: SEIKO EPSON CORPORATION

Inventor： Yoichi Naganuma ,  Eiju Hirai ,  Toshiaki Hamaguchi ,  Motoki Takabe

IPC: B41J2/14 ,  B81C3/00 ,  B41J2/16

CPC classification number: B41J2/14233 ,  B41J2/161 ,  B41J2/1623 ,  B41J2/1628 ,  B41J2/1632 ,  B41J2/164 ,  B41J2002/14241 ,  B41J2002/14362 ,  B81B2201/052 ,  B81C3/001 ,  B81C2203/032

Abstract: A MEMS device includes a first substrate and a second substrate that is disposed laminated on the first substrate and has a piezoelectric element on the first substrate side, in which the first substrate and the second substrate are substantially the same size, and in planar view, an end of the first substrate and an end of the second substrate are disposed at substantially the same position.

公开(公告)号：US09856140B2

公开(公告)日：2018-01-02

申请号：US14512105

申请日：2014-10-10

Applicant: OCE-TECHNOLOGIES B.V.

Inventor： Maikel A. J. Huygens ,  René J. Van Der Meer ,  Reinier Pannekoek ,  Alex N. Westland

IPC: G01R31/02 ,  B81C99/00 ,  B81B7/00 ,  B81C1/00 ,  G01R31/26 ,  H05K1/11 ,  B41J2/14 ,  B41J2/16 ,  H05K1/02

CPC classification number: B81C99/004 ,  B41J2/14233 ,  B41J2/161 ,  B41J2/1632 ,  B41J2/1635 ,  B41J2002/14241 ,  B41J2002/14459 ,  B41J2002/14491 ,  B81B7/007 ,  B81B2201/052 ,  B81B2207/03 ,  B81C1/00301 ,  G01R31/02 ,  G01R31/2601 ,  H05K1/0268 ,  H05K1/111 ,  H05K2201/09372

Abstract: A substrate plate is provided for at least one MEMS device to be mounted thereon. The MEMS device has a certain footprint on the substrate plate, and the substrate plate has a pattern of electrically conductive leads to be connected to electric components of the MEMS device. The pattern forms contact pads within the footprint of the MEMS device and includes at least one lead structure that extends on the substrate plate outside of the footprint of the MEMS device and connects a number of the contact pads to an extra contact pad. The lead structure is a shunt bar that interconnects a plurality of contact pads of the MEMS device and is arranged to be removed by means of a dicing cut separating the substrate plate into a plurality of chip-sized units. At least a major part of the extra contact pad is formed within the footprint of one of the MEMS devices.

公开(公告)号：US09707557B2

公开(公告)日：2017-07-18

申请号：US14486290

申请日：2014-09-15

Applicant: Cambridge Enterprise Limited

Inventor： Wolfgang Andreas Bauer ,  Wilhelm T. S. Huck ,  Martin Fischlechner

IPC: F15C1/02 ,  B01L3/00 ,  B05D7/22 ,  B05C7/04 ,  B81C1/00 ,  B01F17/00

CPC classification number: B01L3/502707 ,  B01F17/00 ,  B01J2219/00511 ,  B01J2219/0059 ,  B01J2219/00637 ,  B01J2219/00783 ,  B01J2219/00788 ,  B01J2219/00831 ,  B01J2219/00833 ,  B01J2219/00837 ,  B01J2219/0097 ,  B01L2200/0636 ,  B01L2300/0867 ,  B01L2300/16 ,  B01L2300/161 ,  B05C7/04 ,  B05D7/22 ,  B05D7/222 ,  B81B2201/0214 ,  B81B2201/05 ,  B81B2201/052 ,  B81B2201/058 ,  B81C1/00119 ,  B81C1/00206 ,  Y10T137/8593

Abstract: We describe a method of layer-by-layer deposition of a plurality of layers of material onto the wall or walls of a channel of a microfluidic device, the method comprising: loading a tube with a series of segments of solution, a said segment of solution bearing a material to be deposited; coupling said tube to said microfluidic device; and injecting said segments of solution into said microfluidic device such that said segments of solution pass, in turn, through said channel depositing successive layers of material to perform said layer-by-layer deposition onto said wall or walls of said channel. Embodiments of the methods are particularly useful for automated surface modification of plastic, for example PDMS (Poly(dimethylsiloxane)), microchannels. We also describe methods and apparatus for forming double-emulsions.

公开(公告)号：US09371225B2

公开(公告)日：2016-06-21

申请号：US14330662

申请日：2014-07-14

Applicant: CANON KABUSHIKI KAISHA

Inventor： Seiko Minami ,  Toshiyasu Sakai

IPC: B81C1/00 ,  H01L21/311 ,  H01L21/3065

CPC classification number: B81C1/00587 ,  B41J2/14145 ,  B41J2/1603 ,  B41J2/1628 ,  B41J2/1631 ,  B41J2/1639 ,  B41J2002/14467 ,  B81B2201/052 ,  B81C1/00087 ,  B81C2201/0132 ,  H01L21/3065 ,  H01L21/30655 ,  H01L21/31116

Abstract: A substrate processing method for forming a through-hole in a substrate by reactive ion etching includes preparing a substrate that has a first surface and a second surface and on the first surface side of which a first layer and a second layer are disposed, the second surface being on the opposite side to the first surface, the second layer covering the first layer; and performing reactive ion etching on the substrate from the second surface to form a through-hole extending through the substrate from the first surface to the second surface, the reactive ion etching being performed to reach the first layer. The etching rate of the second layer for the reactive ion etching is lower than that of the first layer.

Abstract translation: 用于通过反应离子蚀刻在衬底中形成通孔的衬底处理方法包括制备具有第一表面和第二表面的衬底，其第一表面侧上设置有第一层和第二层，第二层 表面位于与第一表面相反的一侧，第二层覆盖第一层; 以及从所述第二表面在所述衬底上进行反应离子蚀刻，以形成从所述第一表面延伸穿过所述衬底到所述第二表面的通孔，进行所述反应离子蚀刻以到达所述第一层。 用于反应离子蚀刻的第二层的蚀刻速率低于第一层的蚀刻速率。

公开(公告)号：US08816450B2

公开(公告)日：2014-08-26

申请号：US13651103

申请日：2012-10-12

Applicant: Panasonic Corporation

Inventor： Masaya Nakatani ,  Hiroshi Ushio ,  Soichiro Hiraoka ,  Akiyoshi Oshima ,  Makoto Takahashi

IPC: H01L27/14 ,  H01L29/82 ,  H01L29/84

CPC classification number: G01N33/48728 ,  B81B2201/0214 ,  B81B2201/052 ,  B81C1/00206 ,  Y10T428/23943

Abstract: A silicon structure of the present invention is provided with a silicon substrate (1) to become a base, and a plurality of fibrous projections (2) made of silicon dioxide and directly joined to a silicon-made surface (1a) of the silicon substrate (1). By arbitrarily constructing an area where these fibrous projections (2) are formed in a predetermined area, it is possible to render the area to have at least either hydrophilicity or water retentivity, so as to provide a silicon structure useful for a variety of devices.

Abstract translation: 本发明的硅结构设置有成为基底的硅基板（1）和由二氧化硅制成的直接接合到硅基板的硅制表面（1a）的多个纤维突起（2） （1）。 通过任意构造这些纤维状突起（2）形成在预定区域的区域，可以使该区域具有至少亲水性或保水性，以提供可用于各种装置的硅结构。

公开(公告)号：US08623674B2

公开(公告)日：2014-01-07

申请号：US13547847

申请日：2012-07-12

Applicant: Masaya Uyama

Inventor： Masaya Uyama

IPC: H01L21/00

CPC classification number: B81C1/00626 ,  B41J2/1404 ,  B41J2/14145 ,  B41J2/1603 ,  B41J2/1628 ,  B41J2/1629 ,  B41J2/1631 ,  B41J2/1645 ,  B41J2/1646 ,  B81B2201/052

Abstract: A liquid ejection head substrate including a silicon substrate having a liquid supply port as hollow and slots as through holes connecting the hollow and a liquid channel arranged opposite sides of the substrate. The method includes etching the substrate to form the hollow; forming a first resist on the hollow; etching the first resist on the bottom of the hollow under conditions of securing an equal etching rate to both the silicon substrate and the first resist; forming a second resist on the hollow; patterning the second resist into an etching mask; and etching the substrate using the etching mask to form the through holes.

Abstract translation: 一种液体喷射头基板，包括具有作为中空的液体供给口的硅基板和作为连接中空部的通孔的槽和布置在基板的相对侧的液体通道。 该方法包括蚀刻基板以形成中空部; 在中空上形成第一抗蚀剂; 在确保与硅衬底和第一抗蚀剂两者相同的蚀刻速率的条件下，蚀刻中空的底部上的第一抗蚀剂; 在中空上形成第二抗蚀剂; 将第二抗蚀剂图案化成蚀刻掩模; 以及使用所述蚀刻掩模蚀刻所述衬底以形成所述通孔。

公开(公告)号：US20130029437A1

公开(公告)日：2013-01-31

申请号：US13547847

申请日：2012-07-12

Applicant: Masaya Uyama

Inventor： Masaya Uyama

IPC: H01L21/00

CPC classification number: B81C1/00626 ,  B41J2/1404 ,  B41J2/14145 ,  B41J2/1603 ,  B41J2/1628 ,  B41J2/1629 ,  B41J2/1631 ,  B41J2/1645 ,  B41J2/1646 ,  B81B2201/052

Abstract: A liquid ejection head substrate including a silicon substrate having a liquid supply port as hollow and slots as through holes connecting the hollow and a liquid channel arranged opposite sides of the substrate. The method includes etching the substrate to form the hollow; forming a first resist on the hollow; etching the first resist on the bottom of the hollow under conditions of securing an equal etching rate to both the silicon substrate and the first resist; forming a second resist on the hollow; patterning the second resist into an etching mask; and etching the substrate using the etching mask to form the through holes.

Abstract translation: 一种液体喷射头基板，包括具有作为中空的液体供给口的硅基板和作为连接中空部的通孔的槽和布置在基板的相对侧的液体通道。 该方法包括蚀刻基板以形成中空部; 在中空上形成第一抗蚀剂; 在确保与硅衬底和第一抗蚀剂两者相同的蚀刻速率的条件下，蚀刻中空的底部上的第一抗蚀剂; 在中空上形成第二抗蚀剂; 将第二抗蚀剂图案化成蚀刻掩模; 以及使用所述蚀刻掩模蚀刻所述衬底以形成所述通孔。

公开(公告)号：US20110024389A1

公开(公告)日：2011-02-03

申请号：US12905078

申请日：2010-10-15

Applicant: Darrell LaRue McReynolds ,  Kia Silverbrook

Inventor： Darrell LaRue McReynolds ,  Kia Silverbrook

IPC: C23F1/00

CPC classification number: H01L21/02057 ,  B41J2/1412 ,  B41J2/1601 ,  B41J2/1623 ,  B41J2/1628 ,  B41J2/1631 ,  B41J2/164 ,  B81B2201/052 ,  B81B2203/033 ,  B81C1/00849 ,  B81C2201/0112 ,  B81C2201/0132

Abstract: A method of etching backside ink supply channels for an inkjet printhead. The method includes the steps of: (a) attaching a frontside of the printhead to a handle wafer; (b) etching the backside of the printhead using an anisotropic DRIE process to form a plurality of ink supply channels, the DRIE process including alternating etching and passivation steps, the passivation steps depositing a polymeric coating on sidewalls of the ink supply channels; and (c) removing the polymeric coating by etching the backside of the printhead in a biased plasma etching chamber using an O2 plasma. The chamber temperature is in the range of 90 to 180° C.

Abstract translation: 一种蚀刻用于喷墨打印头的背面供墨通道的方法。 该方法包括以下步骤：（a）将打印头的前侧连接到手柄晶片; （b）使用各向异性DRIE工艺蚀刻打印头的背面以形成多个供墨通道，所述DRIE工艺包括交替的蚀刻和钝化步骤，所述钝化步骤在所述供墨通道的侧壁上沉积聚合物涂层; 和（c）通过使用O 2等离子体在偏压等离子体蚀刻室中蚀刻打印头的背面去除聚合物涂层。 室温度在90至180℃的范围内

公开(公告)号：US07881594B2

公开(公告)日：2011-02-01

申请号：US12005862

申请日：2007-12-27

Applicant: Ming Fang ,  Fuchao Wang

Inventor： Ming Fang ,  Fuchao Wang

IPC: F24H1/10

CPC classification number: B81C1/00119 ,  B41J2/14056 ,  B41J2/14072 ,  B41J2/14137 ,  B41J2/16 ,  B41J2/1601 ,  B41J2/1628 ,  B41J2/1629 ,  B41J2/1639 ,  B81B1/006 ,  B81B2201/052 ,  B81B2201/058 ,  B81C2201/013 ,  B81C2203/075 ,  H01L28/20 ,  Y10T29/41 ,  Y10T29/49401 ,  Y10T29/49826

Abstract: An integrated semiconductor heating assembly includes a semiconductor substrate, a chamber formed therein, and an exit port in fluid communication with the chamber, allowing fluid to exit the chamber in response to heating the chamber. The integrated heating assembly includes a first heating element adjacent the chamber, which can generate heat above a selected threshold and bias fluid in the chamber toward the exit port. A second heating element is positioned adjacent the exit port to generate heat above a selected threshold, facilitating movement of the fluid through the exit port away from the chamber. Addition of the second heating element reduces the amount of heat emitted per heating element and minimizes thickness of a heat absorption material toward an open end of the exit port. Since such material is expensive, this reduces the manufacturing cost and retail price of the assembly while improving efficiency and longevity thereof.

Abstract translation: 集成半导体加热组件包括半导体衬底，形成在其中的腔室以及与腔室流体连通的出口，允许流体响应于加热室而离开腔室。 集成加热组件包括邻近腔室的第一加热元件，该第一加热元件可以产生高于选定阈值的热量，并将腔室中的流体朝向出口偏压。 第二加热元件邻近出口定位以产生高于所选阈值的热量，便于流体通过出口远离腔室的运动。 添加第二加热元件减少了每个加热元件发出的热量，并使吸热材料的厚度最小化到出口的开口端。 由于这样的材料是昂贵的，所以这降低了组件的制造成本和零售价格，同时提高了其效率和使用寿命。

公开(公告)号：US07850284B2

公开(公告)日：2010-12-14

申请号：US11779085

申请日：2007-07-17

Applicant: David L. Bernard ,  John W. Krawczyk ,  Andrew L. McNees

Inventor： David L. Bernard ,  John W. Krawczyk ,  Andrew L. McNees

IPC: B41J2/05

CPC classification number: B41J2/1603 ,  B41J2/1628 ,  B81B2201/052 ,  B81C1/00087

Abstract: A method of micro-machining a semiconductor substrate to form one or more through slots therein. The semiconductor substrate has a device side and a fluid side opposite the device side. The method includes diffusing a p-type doping material into the device side of the semiconductor substrate in one or more through slot locations to be etched through a thickness of the substrates. The semiconductor substrate is then etched with a dry etch process from the device side of the substrate to the fluid side of the substrate so that one or more through slots having a reentrant profile are formed in the substrate.

Abstract translation: 一种微加工半导体衬底以在其中形成一个或多个通孔的方法。 半导体衬底具有与器件侧相对的器件侧和流体侧。 该方法包括将p型掺杂材料扩散到半导体衬底的一个或多个通孔位置的器件侧，以通过衬底的厚度进行蚀刻。 然后用干蚀刻工艺将半导体衬底从衬底的器件侧蚀刻到衬底的流体侧，使得在衬底中形成具有折入轮廓的一个或多个通槽。