公开(公告)号：WO1993021689A2

公开(公告)日：1993-10-28

申请号：PCT/US1993003536

申请日：1993-04-14

Applicant: ANALOG DEVICES, INC. ,  GILBERT, Barrie

Inventor： ANALOG DEVICES, INC.

IPC: H03G07/00

CPC classification number: H03G7/001

Abstract: A logarithmic amplifier gain stage for supplying, in response to an instantaneous input signal, an output signal corresponding to a logarithmic value of the input signal. The gain stage includes a transistor amplifier having an input that receives the input signal and an intermediate output that supplies an intermediate output signal. A full-wave detector having an input coupled to the intermediate output of the transistor amplifier receives the intermediate output signal and supplies the output signal wherein the detector includes a rectifier comprising transistors having different effective emitter areas. A topology for a logarithmic amplifier is also provided, including a first series-coupled chain of N gain stages having a first input, a second series-coupled chain of M gain stages having a second input, an attenuator coupled between the first input and the second input, a series-coupled chain of summers, each summer receiving an output signal from a respective gain stage in the first series-coupled chain and the second series-coupled chain and supplying a summed signal. A circuit including an output amplifier having an inverting input and a non-inverting input, the inverting input receiving an output of the plurality of gain stages, the non-inverting input receiving a voltage having a negative coefficient of temperature, the output amplifier providing at an output thereof the output signal having a temperature-stable log intercept.

Abstract translation: 对数放大器增益级，用于响应于瞬时输入信号，提供与输入信号的对数值相对应的输出信号。 增益级包括具有接收输入信号的输入的晶体管放大器和提供中间输出信号的中间输出。 具有耦合到晶体管放大器的中间输出的输入的全波检测器接收中间输出信号并提供输出信号，其中检波器包括具有不同有效发射极区域的晶体管的整流器。 还提供了一种用于对数放大器的拓扑，包括具有第一输入的N个增益级的第一串联耦合链，具有第二输入的M个增益级的第二串联耦合链，耦合在第一输入和第 第二输入，串联耦合的夏季链，每个夏天接收来自第一串联耦合链和第二串联耦合链中的相应增益级的输出信号，并提供相加的信号。 一种包括具有反相输入和非反相输入的输出放大器的电路，所述反相输入接收所述多个增益级的输出，所述非反相输入接收具有负的系数温度的电压，所述输出放大器提供在 其输出具有温度稳定的对数截距的输出信号。

公开(公告)号：WO1993021536A1

公开(公告)日：1993-10-28

申请号：PCT/US1993003179

申请日：1993-04-05

Applicant: ANALOG DEVICES, INC.

Inventor： ANALOG DEVICES, INC. ,  CORE, Theresa, A. ,  HOWE, Roger, T.

IPC: G01P15/08

CPC classification number: B81C1/0092 ,  B81B2201/0235 ,  B81C1/00928 ,  B81C99/004 ,  G01P15/0802 ,  G01P15/125 ,  G01P15/131 ,  G01P2015/0814

Abstract: A suspended microstructure fabrication process. Photoresist pedestals (38a) are inserted in a sacrificial layer (30) between the suspended microstructure (20) and the substrate (14) and photoresist spacers (38) are inserted in the microstructure layer between non-contacting portions of the suspended microstructure so that the photoresist pedestals and spacers support the microstructure bridge during the wet etching and drying process used to remove the sacrificial layer.

Abstract translation: 悬浮微结构制造工艺。 将光阻基座（38a）插入在悬浮微结构（20）和衬底（14）之间的牺牲层（30）中，并且将光致抗蚀剂间隔物（38）插入悬浮微结构的非接触部分之间的微结构层中，使得 在用于去除牺牲层的湿蚀刻和干燥过程期间，光致抗蚀剂基座和间隔件支撑微结构桥。

公开(公告)号：WO1993014564A1

公开(公告)日：1993-07-22

申请号：PCT/US1993000162

申请日：1993-01-08

Applicant: ANALOG DEVICES, INC.

Inventor： ANALOG DEVICES, INC. ,  SPITALNY, Paul ,  MALLISON, Martin

IPC: H03G03/00

CPC classification number: H03G3/001 ,  H03G1/0088

Abstract: A programmable gain amplifier including first (10) and second (15) gain elements are connected by an impedance selector (14B) which allows programmability of the gain of both gain elements. The impedance selector (14B) is connected in series with the output of the first gain element (10). The impedance selector (14B) places an impedance in the feedback path of the first gain element (10) or the input path of the second gain element (15). Errors introduced in the signal path due to the switches (S1...SN) are attenuated by the open loop gain of the first gain element. The gain may be equally divided between both stages of the amplifier to allow for optimum bandwidth. Optimum noise performance may be obtained by placing most of the gain in the first stage. An instrumentation amplifier may also be made which further includes a third gain element (18) connected to the gain element with a second impedance selector (19) in a manner similar to the connection of the first gain element (10) to the second gain element (15).

公开(公告)号：WO1992003824A1

公开(公告)日：1992-03-05

申请号：PCT/US1991006068

申请日：1991-08-23

Applicant: ANALOG DEVICES, INC.

Inventor： ANALOG DEVICES, INC. ,  KOKER, Gregory, T.

IPC: G11C07/00

CPC classification number: G11C7/22 ,  G11C7/14 ,  G11C8/18

Abstract: A sense enable timing circuit for addressing data locations in a static random access memory (RAM) array provides a plurality of memory cells formed into a dummy row and a dummy column that is connected to a memory cell at a far end opposite an X-decoder input of said dummy row. The dummy row and column are constructed in conjunction on the same semiconductor chip with a RAM array comprising a plurality of memory cells formed into rows and columns. The dummy column connects to a dummy word line of the dummy row and includes dummy bit lines. Each of the dummy word and bit lines are separate from the word lines and bit lines of the array. The dummy word line is addressed at a time synchronized with the addressing of the array word lines. The occurence of a predetermined voltage change on at least one of the dummy bit lines, carrying a signal of at least one memory cell of the dummy column, is determined in response to the addressing of the dummy word line. In response to this determination, the sensing of array bit line signal is enabled. The signal carried by the dummy bit line may be generated by a plurality of adjacent memory cells. Furthermore, the circuit may include a circuit responsive to the enabling of sensing that amplifies the voltage difference between complementary high and low bit line outputs of the RAM array so that they may equal standard logic values. It may further include a signal generated in response to the predetermined voltage change that deactivates the generation of the bit line signal by a word line.

公开(公告)号：WO1992000558A2

公开(公告)日：1992-01-09

申请号：PCT/US1991004648

申请日：1991-06-28

Applicant: ANALOG DEVICES, INC.

Inventor： ANALOG DEVICES, INC. ,  KOKER, Gregory, T. ,  TSANG, Steven, T.

IPC: G06F01/04

CPC classification number: G06F1/10 ,  G06F1/06 ,  H03D13/004 ,  H03K5/13 ,  H03K5/26 ,  H03L7/0812 ,  H03L7/0895 ,  H03L7/0896

Abstract: A phase detector circuit is provided for correction of operation of a synchronous delay line clock generator. The phase detector includes multiple edge detectors (144, 146, 148). The multiple edge detectors provide an override of any corrective action by the rest of the phase detector to the synchronous delay line output, notwithstanding presence or absence of any phase error of less than 360 DEG , if the phase position of the delay line output signal is off by an integral multiple of 360 DEG . Multiple taps (TAP 2, TAP 9, TAP 14), from daisy-chained or series-connected delay line elements are provided to the multiple edge detectors. The multiple edge detectors compare the edge produced by each such tap against one division of a divided clock signal. Apparatus and method are provided for saving a control signal for a signal-controlled system. A control signal is provided to a multiplexer, which normally produces that control signal. That control signal is digitized and stored by a storage device. The output of the storage device is provided both to the multiplexer and to a comparator. The comparator also receives the output of the multiplexer, and compares the output of the storage device and the multiplexer. The comparator provides a signal to the storage device to increment or decrement the storage device.

Abstract translation: 提供了相位检测器电路，用于校正同步延迟线时钟发生器的操作。 相位检测器包括多个边缘检测器（144,146,148）。 如果延迟线输出信号的相位位置为0°，则多边缘检测器可以将相位检测器的其余部分对同步延迟线输出进行任何校正动作的覆盖，尽管存在或不存在小于360°的任何相位误差 360度的整数倍。 将多个抽头（TAP 2，TAP 9，TAP 14）从菊花链或串联连接的延迟线元件提供给多个边缘检测器。 多边缘检测器将由每个这样的抽头产生的边缘与划分的时钟信号的一个划分进行比较。 提供了用于保存用于信号控制系统的控制信号的装置和方法。 控制信号被提供给多路复用器，其通常产生该控制信号。 该控制信号由存储装置数字化并存储。 存储设备的输出提供给多路复用器和比较器。 比较器还接收多路复用器的输出，并比较存储设备和多路复用器的输出。 比较器向存储设备提供信号以使存储设备递增或递减。

公开(公告)号：WO1991018355A1

公开(公告)日：1991-11-28

申请号：PCT/US1991003199

申请日：1991-05-08

Applicant: ANALOG DEVICES, INC.

Inventor： ANALOG DEVICES, INC. ,  HARSTON, Steven, W. ,  LEONARD, Judson, S.

IPC: G06F15/353

CPC classification number: G06F17/17

Abstract: An interpolator circuit is formed from a chain of multiplexer/adder circuits. Each multiplexer/adder circuit selects one of the two multi-bit binary values which are to be interpolated in accordance with one bit of a multi-bit ratio value. The selected value is shifted and added to the output of a previous stage in the chain. When one of the two values is injected into the first stage, the final sum generated by the circuit chain is the interpolated value.

公开(公告)号：WO1991011863A1

公开(公告)日：1991-08-08

申请号：PCT/US1991000686

申请日：1991-01-31

Applicant: ANALOG DEVICES, INC.

Inventor： ANALOG DEVICES, INC. ,  FERGUSON, Paul, F., Jr. ,  GANESAN, Apparajan ,  ADAMS, Robert, W.

IPC: H03M03/02

CPC classification number: H03G3/02 ,  H03M3/43 ,  H03M3/446 ,  H03M3/45 ,  H03M3/454 ,  H03M7/3028 ,  H03M7/3035 ,  H03M7/304

Abstract: A separate filter circuit (1512, 1522, 1532) is inserted between the D/A converter and the summing junction in the feedback path of a conventional sigma delta modulator. This additional filter allows control of the quantization noise transfer function profile independently of the forward signal transfer function. By proper tailoring of the transfer functions a third or higher order modulator can be constructed without instability developing. The modulator can also be constructed as a completely digital circuit and used as a noise shaping circuit in a digital digital-to-analog converter.

Abstract translation: 在常规Σ-Δ调制器的反馈路径中的D / A转换器和求和结点之间插入单独的滤波器电路（1512,1522,1532）。 该附加滤波器允许独立于正向信号传递函数来控制量化噪声传递函数谱。 通过适当调整传递函数，可以构建第三个或更高阶的调制器，而不会产生不稳定的发展。 调制器也可以构造为完全数字电路，并用作数字数/模转换器中的噪声整形电路。

公开(公告)号：WO1991005404A2

公开(公告)日：1991-04-18

申请号：PCT/US1990005189

申请日：1990-09-13

Applicant: ANALOG DEVICES, INC.

Inventor： ANALOG DEVICES, INC. ,  REAL, Peter ,  ROBERTSON, David, H.

IPC: H03F03/345

CPC classification number: H03F3/345 ,  G05F3/262

Abstract: A cascoded current mirror (11) wherein provision is made for connection, such a buffering connection (17, 19), between the cascode portions (23, 13) of the current mirror (11) to provide feedback between such portions.

公开(公告)号：WO1990004186A1

公开(公告)日：1990-04-19

申请号：PCT/US1989001778

申请日：1989-04-27

Applicant: ANALOG DEVICES, INC.

Inventor： ANALOG DEVICES, INC. ,  BARROW, Jeffrey, George

IPC: G01R13/34

CPC classification number: G01R19/25 ,  G11C27/02

Abstract: A repetitive wave sampler suited to monolithic integrated circuit fabrication, comprising a comparator followed by a master/slave latch feeding into an integrator. The inputs of the comparator are connected to (a) an unknown repetitive waveform having a known frequency and (b) the output of the integrator, which is provided to the comparator through a feedback loop. The master/slave latch is controlled by a clock pulse having a frequency equal to the frequency of the unknown waveform. The master latch is activated on the rising edge of the clock pulse while the slave latch is activated on the falling edge of the clock pulse. The integration performed on the output of the slave latch causes the output voltage of the integrator (i.e., the output of the circuit) to approach the point being sampled on the unknown input waveform. The output voltage will eventually settle to within a preset error range of the input point being sampled.

公开(公告)号：WO1989007793A1

公开(公告)日：1989-08-24

申请号：PCT/US1989000330

申请日：1989-01-26

Applicant: ANALOG DEVICES, INC.

Inventor： ANALOG DEVICES, INC. ,  LEWIS, Stephen, R. ,  BROKAW, A., Paul

IPC: G05F03/30

CPC classification number: G05F3/30 ,  Y10S323/907

Abstract: A bipolar bandgap reference circuit employing three resistors of selected nominal resistance values and a method of trimming the values of two of the resistors to cancel the slope and curvature of output voltage due to thermal drift. One of the resistors provides a positive temperature coefficient to counter the temperature dependency of bipolar base-emitter characteristics; this resistor is not trimmed. The other two resistors are thin-film, low TC devices and are "trimmed" (i.e., adjusted) sequentially, to match calculated values intended to minimize the first and second derivatives of the bandgap cell output, as a function of temperature.