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    SYSTEME DE MICROCALCULATEUR A BUS MULTIPLE AVEC ARBITRAGE D'ACCES AUX BUS.
    143.
    发明专利
    SYSTEME DE MICROCALCULATEUR A BUS MULTIPLE AVEC ARBITRAGE D'ACCES AUX BUS. 未知

    公开(公告)号：BE1002405A4

    公开(公告)日：1991-01-29

    申请号：BE8900435

    申请日：1989-04-20

    Applicant: IBM

    Inventor： BLAND PATRICK MAURICE ,  DEAN MARK EDWARD ,  MILLING PHILIP ERNA

    IPC: G06F9/44 ,  G06F9/445 ,  G06F13/36 ,  G06F13/362

    Abstract: Un système de micro-calculateur à bus multiple comprend un sous système d'antémémoire et un superviseur d'arbitrage. Une unité CPU est prévu avec une source de signaux PREEMPT qui génère un signal de péemption dans des cycles CPU dépassant une durée spécifiée. Le signal de préemption peut s'appliquer à n'importe quel dispositif ayant accès au bus pour initier la fin de l'usage du bus. Lorsque ce dispositif signale sa fin d'usage du bus, le superviseur d'arbitrage change l'état d'un conducteur d'attribution d'arbitrage qui était en phase d'attribution, en phase d'arbitrage. Pendant la phase d'arbitrage, chacun des dispositifs (autres que l'unité CPU) coopère dans un mécanisme d'arbitrage d'usage du bus pendant la phase d'attribution suivante. D'autre part, l'unité CPU ayant revendiqué la préemption, répond à un signal indiquant l'amorçage de la phase d'arbitrage en accédant immédiatement au bus de système.

    CIRCUIT ARRANGEMENT FOR HOLDING AND CLOSING MICROPROCESSORS
    144.
    发明专利
    CIRCUIT ARRANGEMENT FOR HOLDING AND CLOSING MICROPROCESSORS 未知

    公开(公告)号：HU903891D0

    公开(公告)日：1990-11-28

    申请号：HU389190

    申请日：1990-06-18

    Applicant: IBM

    Inventor： BEGUN RALPH MURRAY ,  BLAND PATRICK MAURICE ,  DEAN MARK EDWARD

    IPC: G06F13/36 ,  G06F13/28 ,  G06F13/362

    Abstract: A logic circuit external to a microprocessor monitors selected processor I/O pins to determine the current processor cycle and, in response to a hold request signal, drives the processor into a hold state at the appropriate time in the cycle. The logic circuit also includes a "lockbus" feature that, when the processor is not idle, "locks" the microprocessor to the local CPU bus for a predetermined period of time immediately after the processor is released from a hold state.

    145.
    发明专利
    未知

    公开(公告)号：DE3481351D1

    公开(公告)日：1990-03-15

    申请号：DE3481351

    申请日：1984-11-14

    Applicant: IBM

    Inventor： DEAN MARK EDWARD ,  MOELLER DENNIS LEE

    IPC: G06F9/46 ,  G06F9/38 ,  G06F11/00 ,  G06F11/07 ,  G06F13/36 ,  G06F15/16 ,  G06F15/177

    Abstract: In a data processing system including a main processor (1) and a co-processor (2), a logic circuit (6) is coupled to receive error and busy outputs of the co-processor to generate an interrupt output on co-incidence of active error and busy signals and to latch the busy signal to the main processor to ensure that the main processor will honour the interrupt before executing another co-processor instruction.

    146.
    发明专利
    未知

    公开(公告)号：AT50371T

    公开(公告)日：1990-02-15

    申请号：AT84113735

    申请日：1984-11-14

    Applicant: IBM

    Inventor： DEAN MARK EDWARD ,  MOELLER DENNIS LEE

    IPC: G06F9/46 ,  G06F9/38 ,  G06F11/00 ,  G06F11/07 ,  G06F13/36 ,  G06F15/16 ,  G06F15/177

    Abstract: In a data processing system including a main processor (1) and a co-processor (2), a logic circuit (6) is coupled to receive error and busy outputs of the co-processor to generate an interrupt output on co-incidence of active error and busy signals and to latch the busy signal to the main processor to ensure that the main processor will honour the interrupt before executing another co-processor instruction.

    147.
    发明专利
    未知

    公开(公告)号：BR8902376A

    公开(公告)日：1990-01-16

    申请号：BR8902376

    申请日：1989-05-24

    Applicant: IBM

    Inventor： BLAND PATRICK MAURICE ,  DEAN MARK EDWARD ,  GAUDENZI GENE JOSEPH ,  KRAMER KEVIN GERRARD ,  TEMPEST SUSAN LYNN

    IPC: G06F11/10 ,  G06F13/38 ,  G06F13/40 ,  H03K3/288 ,  H03K19/082 ,  H03M13/00

    Abstract: A circuit for buffering and parity checking digital data communicated between first and second data buses includes a plurality of bidirectional bit buffer circuits. Each of the bidirectional bit buffer circuits includes : a first data path comprising a data receiver, latch, and driver connected in series between the first and second data buses, respectively; a second data patch comprising a data receiver, latch and driver connected in series between the second and first data buses, respectively; control mechanism for controlling the drivers to selectively place the output of the drivers in an active driving or high impedance state; and control mechanisms for controlling the data latches to selectively latch or pass through data. A parity generating circuit is connected at the output of the latch in the first data path of each of the bidirectional bit buffer circuits for generating a parity bit responsive to the data at the output of these latches. A transparent and driver circuit with phase splitter are provided for increasing the speed of the circuit without substantially increasing the power requirements.

    METHOD AND APPARATUS FOR SELECTIVELY POSTING WRITE CYCLES USING THE 82385 CACHE CONTROLLER
    148.
    发明专利
    METHOD AND APPARATUS FOR SELECTIVELY POSTING WRITE CYCLES USING THE 82385 CACHE CONTROLLER 未知

    公开(公告)号：AU3409889A

    公开(公告)日：1989-11-30

    申请号：AU3409889

    申请日：1989-05-05

    Applicant: IBM

    Inventor： BEGUN RALPH MURRAY ,  BLAND PATRICK MAURICE ,  DEAN MARK EDWARD

    IPC: G06F12/08 ,  G06F13/14

    Abstract: A microcomputer system includes a microprocessor, a cache memroy, and a cache controller all coupled to a local bus. The local bus is coupled to a sytem bus, connecting the remaining system components, through latches. When writing data, the microcomputer can perform a posted write to a unit on the system bus by writing the data into the latches and then, on receipt of a ready signal from the cache controller, continuing its operations without waiting for the data to pas to its destination. A problem arises if the data is posted to a unit with a data width less than that of the microprocessor. In this case, the data should be sent in multiple cycles, but the read signal is generated before the data width of the unit is known and the microprocessor then continues its operations and can not, therefore, transmit the data correctly. To solve this problem, a logic unit is added to monitor the ready signal and the output of a decoder which detects non-cacheable addresses (which are of data width different from the microprocessor data width). If a non-cacheable address is detected, the read signal from the cache controller through the logic unit is withheld from the microprocessor, which now waits to continue processing beyond the write until a ready signal is received from the addressed unit on the system bus.

    MICROCOMPUTER SYSTEM INCORPORATING A CACHE SUBSYSTEM USING POSTED WRITES
    149.
    发明专利
    MICROCOMPUTER SYSTEM INCORPORATING A CACHE SUBSYSTEM USING POSTED WRITES 未知

    公开(公告)号：GB2219107A

    公开(公告)日：1989-11-29

    申请号：GB8904918

    申请日：1989-03-03

    Applicant: IBM

    Inventor： BEGUN RALPH MURRAY ,  BLAND PATRICK MAURICE ,  DEAN MARK EDWARD

    IPC: G06F12/08

    Abstract: A microcomputer system includes a microprocessor, a cache memroy, and a cache controller all coupled to a local bus. The local bus is coupled to a sytem bus, connecting the remaining system components, through latches. When writing data, the microcomputer can perform a posted write to a unit on the system bus by writing the data into the latches and then, on receipt of a ready signal from the cache controller, continuing its operations without waiting for the data to pas to its destination. A problem arises if the data is posted to a unit with a data width less than that of the microprocessor. In this case, the data should be sent in multiple cycles, but the read signal is generated before the data width of the unit is known and the microprocessor then continues its operations and can not, therefore, transmit the data correctly. To solve this problem, a logic unit is added to monitor the ready signal and the output of a decoder which detects non-cacheable addresses (which are of data width different from the microprocessor data width). If a non-cacheable address is detected, the read signal from the cache controller through the logic unit is withheld from the microprocessor, which now waits to continue processing beyond the write until a ready signal is received from the addressed unit on the system bus.

    150.
    发明专利
    未知

    公开(公告)号：NO891585L

    公开(公告)日：1989-11-27

    申请号：NO891585

    申请日：1989-04-18

    Applicant: IBM

    Inventor： MILLING PHILIP ERNA ,  BLAND PATRICK MAURICE ,  DEAN MARK EDWARD

    IPC: G06F9/44 ,  G06F9/445 ,  G06F13/36 ,  G06F13/362 ,  G06F12/06 ,  G06F13/38

    Abstract: A multi-bus microcomputer system includes a cache subsystem and an arbitration supervisor. A CPU is provided with a PREEMPT signal source which generates a preempt signal in CPU cycles extending beyond a specified duration. The preempt signal is effective at any device having access to the bus to initiate an orderly termination of the bus usage. When that device signals its termination of bus usage, the arbitration supervisor changes the state of an ARB/GRANT conductor, which had been in the grant phase, to the arbitration phase. During the arbitration phase each of the devices (other than the CPU) cooperates in an arbitration mechanism for bus usage during the next grant phase. On the other hand, the CPU, having asserted preempt, responds to a signal indicating initiation of the arbitration phase by immediately accessing the system bus.

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