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公开(公告)号：CA2065997C
公开(公告)日：1998-02-17
申请号：CA2065997
申请日：1992-04-14
Applicant: IBM
Inventor： HERNANDEZ LUIS ANTONIO , MATHISEN ERIC , MOELLER DENNIS LEE , RAYMOND JONATHAN HENRY , TASHAKORI ESMAEIL , FUOCO DANIEL PAUL
Abstract: This invention relates to personal computers, and more particularly to personal computers in which capability is provided for the usual system controlling processor to be reset, initialized and then isolated if an alternate system controller is provided for the system. In accordance with this invention, a personal computer system has a high speed local processor data bus; an input/output data bus; a microprocessor coupled directly to the local processor bus; a connector coupled directly to the local processor bus for accommodating reception of an alternate processor; and a bus interface controller coupled directly to the local processor bus and directly to the input/output data bus for providing communications between the local processor bus and the input/output data bus, with the bus interface controller providing for detection of the presence of an alternate processor received in the connector and, in response to detection of the presence of an alternate processor, transferring control of the local processor bus from the microprocessor to the alternate processor.
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公开(公告)号：SG43708A1
公开(公告)日：1997-11-14
申请号：SG1996000010
申请日：1993-02-16
Applicant: IBM
Inventor： BLACKLEDGE JOHN WILEY JR , CLARKE GRANT LEACH JR , DAYAN RICHARD ALAN , LE DO KIMTHANH , MCCOURT PATRICK EDWARD , MITTELSTEDT MATTHEW TODD , MOELLER DENNIS LEE , NEWMAN PALMER EUGENE , RANDALL DENNIS LEE , YODER JOANNA BERGER
Abstract: This invention relates to personal computer systems and, more particularly, to such a system having security features enabling control over access to data retained in such a system. In particular, a personal computer system in accordance with this invention has a normally closed enclosure, an erasable memory element for selective activation to active and inactive states and for receiving and storing a privileged access password when in the active state, an option switch operatively connected with the erasable memory element for setting the erasable memory element to the active and inactive states, a tamper detection switch operatively connected with the erasable memory element for detecting opening of the enclosure and for clearing any stored privileged access password from the erasable memory element in response to any switching of the tamper switch, and a system processor operatively connected with the erasable memory element for controlling access to at least certain levels of data stored within the system by distinguishing between the active and inactive states of the memory element and between entry and non-entry of any stored privileged access password. In the presently preferred form of the invention, two non-volatile erasable memory elements are provided, one an EEPROM and the other battery backed CMOS RAM.
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公开(公告)号：IN179597B
公开(公告)日：1997-10-25
申请号：IN441MA1991
申请日：1991-06-10
Applicant: IBM
Inventor： FUOCO DANIEL PAUL , HERNANDEZ LUIS ANTONIO , MATHISEN ERIC , MOELLER DENNIS LEE , RAYMOND JONATHAN HENRY , TASHAKORI ESMAEIL
IPC: G06F1/24
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公开(公告)号：FI922351A0
公开(公告)日：1992-05-22
申请号：FI922351
申请日：1992-05-22
Applicant: IBM
Inventor： FUOCO DANIEL PAUL , HERNANDEZ LUIS ANTONIO , MATHISEN ERIC , MOELLER DENNIS LEE , RAYMOND JONATHAN HENRY , TASKHAKORI ESMAEIL
IPC: G06F13/362 , G06F13/40 , G06F
Abstract: This invention relates to personal computers, and more particularly to personal computers in which performance is enhanced by enabling arbitration for control over a local processor bus among a plurality of "master" devices coupled directly to the local processor bus. A personal computer system in accordance with this invention has a high speed local processor data bus; an input/output data bus; at least two master devices coupled directly to the local processor bus; and a bus interface controller coupled directly to the local processor bus and directly to the input/output data bus for providing communications between the local processor bus and input/output data bus, with the bus interface controller providing for arbitration among the master devices coupled directly to the local processor bus for access to the local processor bus, and providing for arbitration among the local processor bus and any devices coupled directly to the input/output data bus for access to the input/output data bus.
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公开(公告)号：DE3481351D1
公开(公告)日：1990-03-15
申请号：DE3481351
申请日：1984-11-14
Applicant: IBM
Inventor： DEAN MARK EDWARD , MOELLER DENNIS LEE
Abstract: In a data processing system including a main processor (1) and a co-processor (2), a logic circuit (6) is coupled to receive error and busy outputs of the co-processor to generate an interrupt output on co-incidence of active error and busy signals and to latch the busy signal to the main processor to ensure that the main processor will honour the interrupt before executing another co-processor instruction.
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Patent Agency Ranking
公开(公告)号：AT50371T
公开(公告)日：1990-02-15
申请号：AT84113735
申请日：1984-11-14
Applicant: IBM
Inventor： DEAN MARK EDWARD , MOELLER DENNIS LEE
Abstract: In a data processing system including a main processor (1) and a co-processor (2), a logic circuit (6) is coupled to receive error and busy outputs of the co-processor to generate an interrupt output on co-incidence of active error and busy signals and to latch the busy signal to the main processor to ensure that the main processor will honour the interrupt before executing another co-processor instruction.
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公开(公告)号：DE3273756D1
公开(公告)日：1986-11-20
申请号：DE3273756
申请日：1982-05-12
Applicant: IBM
Inventor： MOELLER DENNIS LEE
Abstract: A bi-directional serial printer has a look-ahead feature which determines the distance between the margin of the line being printed and the margin, in the direction of the print head travel, of the next line to be printed. if this distance is less than a predetermined number, print head motion continues after printing the last character on the present line until the print head reaches the margin position for the next line.
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公开(公告)号：ZA85183B
公开(公告)日：1985-11-27
申请号：ZA85183
申请日：1985-01-08
Applicant: IBM
Inventor： DEAN MARK EDWARD , MOELLER DENNIS LEE
Abstract: A microcomputer system includes a main processor (1), a memory (3) and a direct memory access controller (DMA;4) effective to control direct data transfer between the memory and input / output devices on channels. Bus control for data transfer is switchable between the DMA and processor by a hold request/acknowledge handshaking sequence between the DMA and processor. A control line (27) from the channels is activated by a peripheral processing device on a channel when it wishes to gain control of the busses for data transfer. Logic means co-act with the handshaking sequence to determine which device gains control of the busses. This logic is responsive to the DMA address enable output (AEN), the hold acknowledge output of the main processor (HLDA) and the channel control line output (-MASTER). When all these are deactivated, control passes to the main processor, when AEN and HLDA only are activated, control passes to the DMA controller and, when all three are activated, control passes to the peripheral processing device.
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公开(公告)号：BR8500945A
公开(公告)日：1985-10-22
申请号：BR8500945
申请日：1985-03-04
Applicant: IBM
Inventor： DEAN MARK EDWARD , MOELLER DENNIS LEE
Abstract: A microcomputer system includes a main processor (1), a memory (3) and a direct memory access controller (DMA;4) effective to control direct data transfer between the memory and input / output devices on channels. Bus control for data transfer is switchable between the DMA and processor by a hold request/acknowledge handshaking sequence between the DMA and processor. A control line (27) from the channels is activated by a peripheral processing device on a channel when it wishes to gain control of the busses for data transfer. Logic means co-act with the handshaking sequence to determine which device gains control of the busses. This logic is responsive to the DMA address enable output (AEN), the hold acknowledge output of the main processor (HLDA) and the channel control line output (-MASTER). When all these are deactivated, control passes to the main processor, when AEN and HLDA only are activated, control passes to the DMA controller and, when all three are activated, control passes to the peripheral processing device.
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公开(公告)号：BR8203723A
公开(公告)日：1983-06-21
申请号：BR8203723
申请日：1982-06-25
Applicant: IBM
Inventor： MOELLER DENNIS LEE
Abstract: A bi-directional serial printer has a look-ahead feature which determines the distance between the margin of the line being printed and the margin, in the direction of the print head travel, of the next line to be printed. if this distance is less than a predetermined number, print head motion continues after printing the last character on the present line until the print head reaches the margin position for the next line.
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