公开(公告)号：US20180190785A1

公开(公告)日：2018-07-05

申请号：US15394833

申请日：2016-12-30

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Wen Hung ,  Chun-Hsien Lin

IPC: H01L29/49 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/4983 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7833 ,  H01L29/7851

Abstract: A semiconductor device including a semiconductor substrate, agate on the semiconductor substrate, a drain doping region in the semiconductor substrate on a first side of the gate, a source doping region in the semiconductor substrate on a second side of the gate, a first spacer structure on a first sidewall of the gate between the gate and the drain doping region, and a second spacer structure on a second sidewall of the gate between the gate and the source doping region. The first spacer structure is composed of a low-k dielectric layer on the first sidewall of the gate and a first spacer material layer on the low-k dielectric layer. The second spacer structure is composed of a second spacer material layer on the second sidewall of the gate.

公开(公告)号：US20180174970A1

公开(公告)日：2018-06-21

申请号：US15894940

申请日：2018-02-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Wen Hung ,  Jia-Rong Wu ,  Yi-Hui Lee ,  Ying-Cheng Liu ,  Chih-Sen Huang

IPC: H01L23/535 ,  H01L29/66 ,  H01L21/8238 ,  H01L21/768 ,  H01L27/092 ,  H01L23/528

CPC classification number: H01L23/535 ,  H01L21/76805 ,  H01L21/76829 ,  H01L21/76895 ,  H01L21/823475 ,  H01L21/823871 ,  H01L23/485 ,  H01L23/528 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L27/092 ,  H01L29/66545

Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate; forming a first gate structure on the substrate, a first spacer around the first gate structure, and an interlayer dielectric (ILD) layer around the first spacer; performing a first etching process to remove part of the ILD layer for forming a recess; performing a second etching process to remove part of the first spacer for expanding the recess; and forming a contact plug in the recess.

公开(公告)号：US20180130742A1

公开(公告)日：2018-05-10

申请号：US15863986

申请日：2018-01-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Ling Lin ,  Chih-Sen Huang ,  Ching-Wen Hung ,  Jia-Rong Wu ,  Tsung-Hung Chang ,  Yi-Hui Lee ,  Yi-Wei Chen

IPC: H01L23/528 ,  H01L27/06 ,  H01L23/532 ,  H01L21/768 ,  H01L21/8234

CPC classification number: H01L23/5283 ,  H01L21/76816 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76897 ,  H01L21/823475 ,  H01L23/53261 ,  H01L23/53266 ,  H01L27/0629

Abstract: A method for fabricating semiconductor device first includes providing a substrate and a shallow trench isolation (STI) in the substrate, in which the substrate includes a first metal gate and a second metal gate thereon, a first hard mask on the first metal gate and a second hard mask on the second metal gate, and a first interlayer dielectric (ILD) layer around the first metal gate and the second metal gate. Next, the first hard mask and the second hard mask as mask are utilized to remove part of the first ILD layer for forming a recess, and a patterned metal layer is formed in the recess and on the STI.

公开(公告)号：US20180040558A1

公开(公告)日：2018-02-08

申请号：US15247948

申请日：2016-08-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Wen Hung ,  Chih-Sen Huang

IPC: H01L23/535 ,  H01L29/423 ,  H01L21/768 ,  H01L21/8234 ,  H01L27/088 ,  H01L27/02

CPC classification number: H01L23/535 ,  H01L21/76895 ,  H01L21/823437 ,  H01L21/823475 ,  H01L27/0207 ,  H01L27/088 ,  H01L29/42356 ,  H01L29/66545

Abstract: A semiconductor device and a method of fabricating the same are provided. The semiconductor device includes a substrate, a plurality of gates and a plurality of plugs. The gates are disposed on the substrate and extend in a first direction. The gates include a first gate and a second gate. The first gate includes a first protruding portion extending in a second direction. The plugs are disposed parallel to one another on the substrate. The plugs include a first plug and a second plug. The first plug and the second plug cover the first gate and the second gate respectively. A central axis of the first plug is shifted from a central axis of the first gate toward the second direction, and a central axis of the second plug is shifted from a central axis of the second gate toward the second direction.

公开(公告)号：US09875941B1

公开(公告)日：2018-01-23

申请号：US15289978

申请日：2016-10-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Wen Hung ,  Chih-Sen Huang

IPC: H01L21/336 ,  H01L21/8234 ,  H01L21/02 ,  H01L21/033

CPC classification number: H01L21/823481 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/0332 ,  H01L21/823431

Abstract: A method for fabricating semiconductor device is disclosed. First, a first fin-shaped structure and a second fin-shaped structure are formed on a substrate, and a shallow trench isolation (STI) is formed around the first fin-shaped structure and the second fin-shaped structure, a patterned hard mask is formed on the STI. Next, part of the first fin-shaped structure and part of the second fin-shaped structure adjacent to two sides of the patterned hard mask are removed for forming a first recess and a second recess, and a dielectric material is formed into the first recess and the second recess.

公开(公告)号：US09870996B1

公开(公告)日：2018-01-16

申请号：US15247948

申请日：2016-08-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Wen Hung ,  Chih-Sen Huang

IPC: H01L21/8234 ,  H01L23/535 ,  H01L27/088 ,  H01L27/02 ,  H01L21/768 ,  H01L29/423

CPC classification number: H01L23/535 ,  H01L21/76895 ,  H01L21/823437 ,  H01L21/823475 ,  H01L27/0207 ,  H01L27/088 ,  H01L29/42356 ,  H01L29/66545

Abstract: A semiconductor device and a method of fabricating the same are provided. The semiconductor device includes a substrate, a plurality of gates and a plurality of plugs. The gates are disposed on the substrate and extend in a first direction. The gates include a first gate and a second gate. The first gate includes a first protruding portion extending in a second direction. The plugs are disposed parallel to one another on the substrate. The plugs include a first plug and a second plug. The first plug and the second plug cover the first gate and the second gate respectively. A central axis of the first plug is shifted from a central axis of the first gate toward the second direction, and a central axis of the second plug is shifted from a central axis of the second gate toward the second direction.

公开(公告)号：US09865593B1

公开(公告)日：2018-01-09

申请号：US15402245

申请日：2017-01-10

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Lin Lu ,  Chun-Lung Chen ,  Kun-Yuan Liao ,  Hsiang-Hung Peng ,  Wei-Hao Huang ,  Ching-Wen Hung ,  Chih-Sen Huang

IPC: H01L27/06 ,  H01L21/8234 ,  H01L21/768 ,  H01L49/02

CPC classification number: H01L27/0629 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76895 ,  H01L21/823431 ,  H01L21/823475 ,  H01L28/20 ,  H01L28/24

Abstract: A method for fabricating semiconductor device is disclosed. A substrate having a first transistor on a first region, a second transistor on a second region, a trench isolation region, a resistor-forming region is provided. A first ILD layer covers the first region, the second region, and the resistor-forming region. A resistor material layer and a capping layer are formed over the first region, the second region, and the resistor-forming region. The capping layer and the resistor material layer are patterned to form a first hard mask pattern above the first and second regions and a second hard mask pattern above the resistor-forming region. The resistor material layer is isotropically etched. A second ILD layer is formed over the substrate. The second ILD layer and the first ILD layer are patterned with a mask and the first hard mask pattern to form a contact opening.

公开(公告)号：US20170287843A1

公开(公告)日：2017-10-05

申请号：US15091562

申请日：2016-04-05

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Jia-Rong Wu ,  Ying-Cheng Liu ,  Ching-Wen Hung ,  Yi-Hui Lee ,  Chih-Sen Huang

IPC: H01L23/532 ,  H01L23/535 ,  H01L27/092

CPC classification number: H01L23/53266 ,  H01L21/285 ,  H01L21/76831 ,  H01L21/76846 ,  H01L21/76865 ,  H01L21/76877 ,  H01L21/823871 ,  H01L23/485 ,  H01L23/53223 ,  H01L23/53238 ,  H01L27/092

Abstract: According to a preferred embodiment of the present invention, a semiconductor device is disclosed. The semiconductor device includes: a substrate having a first region and a second region; a first contact plug on the first region, and a second contact plug on the second region. Preferably, the first contact plug includes a first interfacial layer having a first conductive type and a first work function metal layer having the first conductive type on the first interfacial layer, and the second contact plug includes a second interfacial layer having a second conductive type and a second work function metal layer having the second conductive type on the second interfacial layer.

公开(公告)号：US20170263597A1

公开(公告)日：2017-09-14

申请号：US15604685

申请日：2017-05-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Wen Hung ,  Chih-Sen Huang ,  Shih-Fang Tzou ,  Yi-Wei Chen ,  Yung-Feng Cheng ,  Li-Ping Huang ,  Chun-Hsien Huang ,  Chia-Wei Huang ,  Yu-Tse Kuo

IPC: H01L27/02 ,  H01L21/8238 ,  H01L29/66 ,  H01L21/768 ,  H01L27/11 ,  H01L27/092

CPC classification number: H01L27/0207 ,  H01L21/768 ,  H01L21/76816 ,  H01L21/76829 ,  H01L21/823821 ,  H01L21/823871 ,  H01L27/0924 ,  H01L27/1104 ,  H01L29/66545 ,  H01L29/6681 ,  H01L29/7851

Abstract: Semiconductor devices and method of manufacturing such semiconductor devices are provided for improved FinFET memory cells to avoid electric short often happened between metal contacts of a bit cell, where the meal contacts are positioned next to a dummy gate of a neighboring dummy edge cell. In one embodiment, during the patterning of a gate layer on a substrate surface, an improved gate slot pattern is used to extend the lengths of one or more gate slots adjacent bit lines so as to pattern and sectionalize a dummy gate line disposed next to metal contacts of an active memory cell. In another embodiment, during the patterning of gate lines, the distances between one or more dummy gates lines disposed adjacent an active memory cell are adjusted such that their locations within dummy edge cells are shifted in position to be away from metal contacts of the active memory cell.

公开(公告)号：US09721841B1

公开(公告)日：2017-08-01

申请号：US15140019

申请日：2016-04-27

Applicant: United Microelectronics Corp.

Inventor： Jun-Jie Wang ,  Yu-Lin Wang ,  Ching-Wen Hung ,  En-Chiuan Liou ,  Chih-Sen Huang

IPC: H01L21/82 ,  H01L21/8234 ,  H01L27/11 ,  H01L27/088 ,  H01L29/49 ,  H01L29/06

CPC classification number: H01L21/823456 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823468 ,  H01L27/0207 ,  H01L27/0886 ,  H01L27/1104 ,  H01L28/00 ,  H01L29/0649 ,  H01L29/4916

Abstract: An electronic circuit includes a plurality of fin lines on a substrate and a plurality of gate lines with a first line width, crossing over the fin lines. The gate lines are parallel and have a plurality of discontinuous regions forming as a plurality of slots. A region of any one of the gate lines adjacent to an unbalance of the slots has a second line width smaller than the first line width.